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我想设置其采样率为983.04M，（经过8倍内插 ，122.88*8）那初始的这个122.88是从哪里来的？ LVDS的器件可以FPGA直接给122.88MSPS的数据随路时钟 这种204B接口的是从哪来？
您好，
您是想要fDATA=122.88MSPS，fDAC=983.04MSPS.
请参考数据手册"7.3.2 Serdes Rate"和“Table 11. DAC38J84 Speed Limits',
Quad-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters datasheet (Rev. B)
