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Original question:

[参考译文] ADS1285：寄存器编程问题

ADS1285: Can I use a 8MHz clock frequency instead of 8.196MHz ? What would this affect ?

? ?
Prodigy 70 points
Part Number: ADS1285

There is a requirement for the ADC clock frequency in ADS1285. The recommended fCLK value is 8.196MHz, but the allowed fCLK range is 6-8.3MHz. Can I provide an 8MHz clock ( generated via PWM from a MCU ) ? How will this affect the operation of the ADC? Sorry, I did not find any description of the clock frequency other than 8.196MHz in the data sheet.

在ADS1285中有对于时钟频率的要求，推荐值是8.196MHz，但允许范围是6-8.3MHz。我能否提供8MHz时钟，这对ADC的工作有何影响？抱歉，我并未在数据手册中找到关于除8.196MHz时钟频率以外的介绍。

  • +1
    TI__Mastermind 34565 points

    Hi,

    Yes, you can use a clock frequency of 8MHz.  This will result in a slightly lower data rate for a given data rate setting.  For example, if the data rate is set to 1000sps and you use an 8MHz input clock frequency, then your actual data rate will be 1000*8/8.192=976.6sps.

    Also, if you only plan to measure DC voltages up to a few Hz, then you can use an MCU clock output as long as the duty cycle is within 44% to 56%.  However, if you want to measure AC signals greater than a few Hz, you need to use a low jitter source clock, such as a good oscillator.

  • 0 回复 Taylor
    Prodigy 70 points

    I used three ADS1285s in my PCB. I configured them to sample at 1000SPS. The actual data output rate detected was 976.6Hz, which is consistent with the expected rate. In my previous test, I used the pulse-sync mode, and the chip drdy frequency was 976.6Hz, which was consistent with the expected rate. Next, I configured the ads1285 to continuous-sync mode, and output a PWM wave through the microcontroller to provide a synchronization signal for the ads1285. The datasheet describes that when the drdy frequency differs from the sync signal frequency by several clock cycles, the ads1285 will resynchronize. During my test, I found that the signal frequency always stay the same as the PWM frequency, unless I output the PWM frequency exceeding 976.6 (which would cause DRDY to fail to output a signal). When my PWM frequency is lower than 976.6, the output drdy signal freq of ADS1285 decreases accordingly. What makes me wonder is whether its sampling rate will decrease at the same time; or only the DRDY signal rate changes, while the internal sampling rate remains unchanged? And when(at which moment?) the sample happened?

    here is the datasheet words:------------------

    8.4.4.2 Continuous-Sync Mode

    After synchronization, DRDY continues to pulse; however, data are held low for 63 data periods to allow for the digital filter to settle. See fig 6-4 for the DRDY behavior. Because of the initial delay of the digital filter, the SYNC input signal and the DRDY pulses exhibit an offset time. The offset time is a function of the data rate.

    -------------------------------------------

    我的PCB中使用了三片ADS1285，我将他们配置为1000SPS采样速率，实际检测到的数据输出速率为976.6Hz，这与预期的速率符合。在我前面的测试中，我使用的是脉冲同步模式(Pulse-Sync Mode)，芯片drdy频率是符合预期的976.6Hz。接下来我将ads1285配置为连续同步模式(Continuous-Sync Mode)，并通过单片机输出一路PWM波，为ads1285提供同步信号。数据手册中描述，当drdy频率与sync信号频率相差为数个时钟周期时，ads1285将发生重新同步。在我测试过程中，我发现信号的频率始终与PWM频率保持相同，除非我输出PWM频率超过了976.6(这会导致DRDY无法输出信号)。当我的PWM频率低于976.6时，ads1285的输出数据速率随之降低，让我疑惑的是其采样速率是会同时降低；还是仅变化了drdy信号速率，而内部采样速率是保持不变的。

  • 0 回复 ? ?
    TI__Mastermind 34565 points

    新问题请重新发帖。