After utilizing your company's analog-to-digital converter ADS1271, we followed the recommended peripheral circuit provided in the instrument datasheet, selected SPI mode and high-resolution mode, and ensured the correct timing of DRDY and SCLK. However, we observed inconsistent idle levels (high/low variations) in the D_OUT signal, leading to extreme fluctuations in the readings. We are deeply perplexed by this issue and seek your technical assistance.
