Part Number: DLP3940S-Q1
Other Parts Discussed in Thread: DLPC231S-Q1,
Dear TI Support Team,
I am currently evaluating the DLP3940S-Q1 chipset (paired with DLPC231S-Q1 controller) for a puddle light application. I have a few questions regarding the system architecture and the resolution accelerator implementation.
1. Is the external FPGA necessary in the application block diagram?
I understand that in the typical HUD reference design, an FPGA is used as a resolution accelerator to convert the 1920×800 orthogonal display input into a diamond-compatible format (quincunx). However, I also noticed that the DLPC231S-Q1 display frame buffer can natively support up to 1,536,000 pixels, and the FPGA's output (2716×1130/2 ≈ 1,534,540 pixels) fits within this limit.
Could you please clarify whether the FPGA is strictly required for the chipset to function, or if it is optional? If it is optional, could you provide more details about the system architecture without the FPGA?
2. How to implement the quincunx conversion on an SoC instead of FPGA?
I saw in the documentation that "this resolution accelerator routine can be offloaded from the FPGA to be performed as a pre-processing step on a high-bandwidth host processor, thereby bypassing and eliminating the need for the FPGA."
Could you please advise on how to implement this quincunx conversion on a typical automotive SoC? What are the minimum performance requirements (e.g., processing bandwidth, memory, GPU computility) for the host processor to handle this preprocessing in real-time?
3. Where can I obtain the quincunx algorithm source code?
I understand from the documentation that "TI provides source code and a royalty-free license to the quincunx algorithm which can be implemented on the domain controller, HUD processor, or FPGA." Could you please provide guidance on how to access this source code? Is it available for download from the TI website, or do I need to request it through an NDA with TI?
Additionally, are there any application notes or reference designs available that demonstrate the quincunx algorithm implementation on an SoC or GPU?
Thank you for your time and support. I am looking forward to your response.
Best regards,
Jason