Part Number: DLPC350
Other Parts Discussed in Thread: DLP4500,
Dear TI expert!
We are using the DLPC350 + DLP4500 for projection design, with the following requirements:
Input graphics via RGB interface only throughout the entire process. Select trigger mode 0, VSYNC triggering, 8-bit pattern, and a total of 3 patterns. The VSYNC period is 16,080 μs.
We expect to output three patterns within one VSYNC cycle. These three patterns correspond respectively to the graphic data inputs of the RGB channels. All three patterns have the same exposure time and are triggered identically by VSYNC.
Our register settings are as follows:
#Write: Set the display mode to pattern display
W 0x34 0x69|0x80 0x01
# Write: Stop Sequence (Display if running)
W 0x34 0x65|0x80 0x00
#Write: Set the graphics display mode source to RGB
W 0x34 0x6f|0x80 0x00
#Write: Set mode number 1 - Mode
W 0x34 0x75|0x80 0x02 0x01 0x02 0x00
#Write: Set mode trigger mode - 0
W 0x34 0x70|0x80 0x00
#Write: Exposure Time
W 0x34 0x66|0x80 0xF0 0x14 0x00 0x00 0xD0 0x3E 0x00 0x00 // 0x3ED0 corresponds to 16080us, 0x14F0 corresponds to 5360us. 5360x3=16080
#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02
#Write: Pat LUT offset //Set the first LUT
W 0x34 0x76|0x80 0x00
#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x28 0x00
#Write: Close email
W 0x34 0x77|0x80 0x00
#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02
#Write: Pat LUT offset //Set the 2nd LUT
W 0x34 0x76|0x80 0x01
#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x18 0x00
#Write: Close email
W 0x34 0x77|0x80 0x00
#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02
#Write: Pat LUT offset //Set the 3rd LUT
W 0x34 0x76|0x80 0x02
#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x48 0x00
#Write: Close email
W 0x34 0x77|0x80 0x00
#Write: Verify LUT
W 0x34 0x7D|0x80 0x00
# Add validation to complete delay or polling status
#Write: Start pattern sequence
W 0x34 0x65|0x80 0x02
After completing the above register settings, we found that the read value of register 0x7D is 0x01. What could be the cause of this issue, and how can it be resolved?
One more point to add: The video stream of the RGB channels we input to the dlpc350 is FPGA-simulated. During the DE active period, the resolution is 1280x800, the data clock of RGB is 72 MHz, and the VSYNC period = 1340x862/72 = 16080 us.
Looking forward to your reply!