Part Number: DLPC350
Dear Technical Expert!
In the document DLPU010G – May 2013 – Revised July 2018, on page 48 of the description of the dlp0x66 register, in the external video input pattern sequence modes, the pattern exposure time must be equal to the frame period.
However, on page 61, in Table 4-2. Trigger Mode 0 Example, for register 0x66, Set the exposure and frame rate (4 bytes for each) so that the time between vsync triggers will allow three patterns to be shown For example,
for a 60-Hz vsync, the maximum exposure time is 16667 ÷ 3.
These two points are clearly in conflict. On page 48, it states that the pattern exposure time must be equal to the frame period. However, on page 61, it says that the time between vsync triggers will allow three patterns to be displayed.
Is "the frame period" here referring to the frame period of VSYNC?
We input the pattern through RGB, and select an 8-bit pattern. Then we have pattern num 1 (green 8-bit), pattern num 2 (red 8-bit), and pattern num 3 (blue 8-bit). In this case, what is the relationship between the pattern exposure time and the frame period? How should the register 0x66 be set?
If the frame period of VSYNC is 12000us, should the pattern exposure time be set to 4000us or 12000us?
How can we project 3 pattern patterns within one VSYNC frame period? These three pattern patterns correspond to the pattern num 1, pattern num 2, and pattern num 3 described in Table 2-70 of Document DLPU010G?
In the above situation, how should the registers 0x75 and 0x78 be set?
Due to the urgency of the project, we hope to receive a reply as soon as possible!