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Original question:

[参考译文] PROCESSOR-SDK-J784S4：CR 阶段的 DP 链路训练失败

DS90UH983-Q1: CR和EQ训练概率性失败

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Prodigy 40 points
Part Number: DS90UH983-Q1

您好：

    我们正在调试983的链路训练功能，发现CR训练有很大概率的训练失败，导致EQ也会训练失败。请问这个会是什么原因导致的呢？这个有什么办法解决和规避吗？我们使用的是8.1Gbps   4-lane工作模式。

  • 0
    TI__Mastermind 29115 points

    您好，

    已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

  • 0
    TI__Mastermind 30300 points

    Who is the tier 1 and OEM?

    In order to properly assist you, I need additional details as DP link training failures can take on various forms. See below:

    1. Is this occurring during init or runtime?
    2. How many units is this impacting out of how many total units?
    3. Roughly how many power cycles does it take to reproduce the CR training issue?
    4. Has the customer monitored APB registers 0x43C and 0x440?
    5. Has the customer monitored APB registers 0x490, 0x494, 0x498, and 0x49C for symbol errors?
    6. Has the customer tried any other link rate, lane rate combos and does this only fail at 4 lanes, 8.1Gbps?