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When DPLL operation is enabled and the DPLL is locked, the DPLL reference inputs (INx pins) determine the frequency stability and accuracy of the output clocks. The clock source on the XO pin determines the free-run and holdover frequency stability and accuracy of the output clocks. The VCBO determines the BAW APLL output clock phase noise and jitter performance over the 12kHz to 20MHz integration band, regardless of the frequency and jitter of the XO pin input.
