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DS280DF810: about the CDR lock of DS280DF810

Part Number: DS280DF810
Other Parts Discussed in Thread: DS280MB810

 if sub-clock(such as sin=1.611328125ghz) is applied on Rx0 channel, Are the channel  of TX0 and TX1 both set at PRBS output through the crossbar function? or  each channel needs the standard data-rata for CDR lock?