Other Parts Discussed in Thread: DP83TC818S-Q1,
Hello, currently I am facing some issues with the DP83TC818EVM-MC evaluation board. This board uses the DP83TC818S-Q1 chip, which is a 100BASE-T1 automotive Ethernet chip. In the description of this chip, I saw "Integrated IEEE802.1AS/IEEE1588v2 hardware timestamp and fractional PLL, enabling highly accurate time synchronization. The fractional PLL can achieve clock frequency and phase synchronization of the clock (without the need for an external VCXO), and can generate various time synchronization frequencies required for audio and other ADAS applications. This PHY also integrates IEEE 1722 CRF decoding, which can generate media clocks and bit clocks for AVB and other audio applications." I have some doubts about the generated clock frequencies. Can the clock frequencies be output at any arbitrary frequency through the hardware timestamp and fractional PLL? If I want to achieve a 66.66 MHz clock output now, can this be done? Also, is the frequency and phase of the output clock synchronized with the reference clock input by the PHY? Or is it synchronized with the 66.66 MHz final data transmission clock of the PHY? Finally, is it connected through the SMA port on the DP83TC818EVM-MC evaluation board? Thank you very much for replying to these questions to assist with the subsequent selection process. Thank you.
