We read all the registers of the PHY chip and all the values are 0xffff.
We looked at this link, but it doesn't work.
We have confirmed that a 50 MHz clock is coming into XI. ( Has power, has reset )
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We read all the registers of the PHY chip and all the values are 0xffff.
We looked at this link, but it doesn't work.
We have confirmed that a 50 MHz clock is coming into XI. ( Has power, has reset )
Can you please send a schematic of your current design?