Part Number: DS90UB941AS-Q1
hardware link：soc-------ds90ub941--------ds90ub948------------lcd
register configuration：
{0x01, 0x08}, //Disable DSI
{0x11, 0x33}, //Disable DSI
{0x5b, 0x10}, //select dsi pll colck
{0x40, 0x04}, //Select DSI Port 0 digital registers
{0x41, 0x20}, //Select DSI_CONFIG_0 register
{0x42, 0x6f}, //Set DSI_SYNC_PULSES = 0
{0x41, 0x21}, //Select DSI_CONFIG_1 register
{0x42, 0x60}, //Set DSI_VS_POLARITY=DSI_HS_POLARITY=1
{0x4f, 0x8c}, //Set DSI_CONTINUOUS_CLOCK, single DSI, 4 lanes, DSI Port 0 input
{0x41, 0x30}, //Select DSI_HSW_CFG_HI register
{0x42, 0x00},
{0x41, 0x31}, //Select DSI_HSW_CFG_LO register
{0x42, 0x18}, //hsync-len = 12
{0x41, 0x32}, //Select DSI_VSW_CFG_HI register
{0x42, 0x00},
{0x41, 0x33}, //Select DSI_VSW_CFG_LO register
{0x42, 0x03}, //hsync-len = 3
{0x40, 0x04}, //Select DSI Port 0 digital registers
{0x41, 0x05}, //TSKIP_CNT set indirect addr (reg DPHY_SKIP_TIMING)
{0x42, 0x2E}, //TSKIP_CNT set reg DPHY_SKIP_TIMING value
{0x40, 0x10},
{0x41, 0x86},
{0x42, 0x0A},
{0x41, 0x94},
{0x42, 0x0A},
{0x0e, 0x3f}, //TP_INT BL_EN
{0x0f, 0x03}, //PWM
{0x10, 0x03}, //TP_RST NULL
{0x01, 0x00} //Enable DSI
Question 1：FREQ_DET_PLL
The difference between DSI clock and DSI PLL clock？
Question 2：
The normal display indicates that the DSI clock is functioning properly. Why is there an abnormal i2c read-write operation
