Part Number: TCAN1463-Q1
Hi TI Experts,
I'm supporting customer CATL who is developing a 12V Battery Management System (BMS) and encountering a critical issue during BCI testing with the TCAN1463-Q1 CAN transceiver. This is blocking their validation timeline and we need urgent technical support.
Problem Description
During Bulk Current Injection (BCI) testing per ISO 11452-4, severe CAN bus malfunction is observed.
Test Conditions:
- Frequency range: 10–20 MHz
- Injection current: 200 mA
- Test method: RF injection directly on CAN bus lines
Critical Symptoms:
- Both CAN_H and CAN_L are pulled down to 0V during injection
- CAN error frames are continuously generated
- Complete communication failure during the test window
Current Hardware Configuration:
- Part number: TCAN1463-Q1
- Termination: 120Ω resistor
- Bus capacitor: 47pF (discrete)
- Common mode choke: 51µH (differential impedance ~9Ω @ 10MHz)
- TVS diode: Parasitic capacitance Cp = 15pF
Technical Questions Requiring TI Guidance
Q1: CAN Error Frame Formation Mechanism
Can you explain the detailed mechanism of error frame generation under RF injection conditions? Customer's current understanding is:
"During RF injection, common-mode disturbances may be converted into differential disturbances at the receiver input, causing false dominant bit detection and triggering CAN error frames."
We need clarification on:
- The voltage threshold for false dominant bit detection
- Relevant specifications in the TCAN1463-Q1 datasheet
- How to systematically evaluate the effectiveness of each proposed mitigation measure
Q2: Discrete Capacitor Value Selection Logic
The interference frequency band is centered around 10 MHz. Based on the customer's design experience, a capacitance of ~100nF would provide better resonance characteristics at this frequency. However, TI's guidance recommends only 1–4.7nF.
- What is the technical rationale behind the 1–4.7nF recommendation?
- Why are higher capacitance values (e.g., 100nF) not recommended?
- Is there a trade-off with signal integrity or bus timing?
Q3: TVS Capacitance Direction — Increase or Decrease?
Following the logic in Q2 regarding capacitive filtering at 10 MHz, should the TVS parasitic capacitance (Cp) actually be increased rather than decreased? Specifically:
- What is the optimal Cp range for suppressing 10–20 MHz interference?
- Is there a fundamental conflict between keeping Cp low for signal integrity and raising Cp for EMI suppression?
Customer's Proposed Mitigation Measures (Need TI Validation)
The customer has proposed three countermeasures and needs technical guidance on feasibility:
1. Common Mode Choke (CMC) Adjustment
- Current: 51µH
- Proposed: Increase to 100µH for better low-frequency EMI suppression
- Concern: Will this degrade signal quality or affect rise/fall time?
2. TVS Parasitic Capacitance Optimization
- Current Cp: ~15pF
- Proposed: Reduce to 5–10pF range
- Question: Is lower capacitance actually beneficial at 10 MHz?
3. Discrete Bus Capacitor Increase
- Current: 47pF (within typical 47–100pF range)
- Proposed: Increase to 100pF
- Limitation: Values of 1–4.7nF are not feasible in current PCB layout
Summary of Support Needed
- Root cause analysis: Why are CAN_H/CAN_L pulled to 0V during 10–20 MHz BCI injection?
- Technical validation of the three proposed mitigation measures
- Design guidelines and recommended component values for TCAN1463-Q1 BCI immunity in the 10–20 MHz range
This issue is blocking CATL's EMC validation testing. Any expedited support is greatly appreciated.
Thank you!
