Part Number: DS90UB981-Q1
DS90UB981-Q1 debugging issue:When using 1clk + 4lane at 1080P@30Hz, the device fails to recognize. The following phenomena occur: all DSI errors are 0, and MEAS_H_TOTAL0_VP0, MEAS_H_TOTAL1_VP0 are also 0. Only DPHY_STATUS can be recognized. When using 1clk + 2lane at 1080P@30Hz, there is an unstable recognition phenomenon. Sometimes it can be recognized during power-on/off, but sometimes it cannot. Only when 1clk + 1lane at 864X480@60Hz can be recognized, this is related to whether the 1 clock and 4 data streams are processed at the same length. Currently, only each differential pair is internally equal in length. Please help figure out the reason and suggest any improvements.
