04828使用0-delay模式,每次上电的输出的时钟和输入的时钟相位差都不一样

jie xu5

04828使用0-delay模式,每次上电的输出的时钟和输入的时钟相位差都不一样,使用的是cascaded 0-delay,

pll1的设置是clkin1=100M.clkin1_r = 100,pll1_pdf = 1M,pll1_N= 125,

pll2的设置是pll2_r = 10,使能了pll2参考2倍,pll2_pdf = 25M,feedback_mux选择的是dclkout8,设置的dclkout8为1.2G,pll2_N= 0x30,pll2_N_cal = 0x30.

两极的pll都锁住了，但是每次上电的输出的时钟和输入的时钟相位差都不一样。求各路高手指导。

9 年多前

0 Kailyn Chen 9 年多前

TI__Guru**** 295050 points

有没有做sync的动作，将Reg 0x143 的bit4=1.

0 jie xu5 9 年多前回复 Kailyn Chen

Prodigy 43 points

没有使用sync,

0-delay模式指的不就是输出和输入的相位差固定吗?按照手册上的手册上的说法

Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock (OSCin) to the phase of a clock selected by the feedback mux. The 0-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX. Because OSCin has a fixed deterministic phase relationship to the feedback clock, OSCout will also have a fixed deterministic phase relationship to the feedback clock. In this mode PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input clock (OSCin), this results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs.

Without using 0-delay mode there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

不知道我的理解是不是正确