Part Number: DS160PR410
Hi, Team
Currently, the overall system signal link is shown in the diagram. The sensor transmits data back to the FPGA at 16 Gbps via the DS160PR410. The FPGA uses Xilinx digital eye diagram IP core for testing. The current test results show that when the value is set to different values, the processing results of the digital eye diagram exhibit inconsistent passband flatness between the left and right half-regions. What could be the possible causes?
