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SN74LVC1G74: Q sometimes show 0V or around 700mV after power-on

xc t
Prodigy 60 points

Part Number: SN74LVC1G74

The application circuit of my SN74LVC1G74DCTR latch uses 100K pull-up to 3.3V for D and PRE#, and CLR# is pulled up to 3.3V with a 100nF capacitor to GND. 1. Why does Q sometimes show 0V or around 700mV after power-on? Changing the 100nF to 10nF improves it a bit, but it still happens. 2. Also, what is the output structure of Q and Q# for this device? It seems not to be push-pull.

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    TI__Mastermind 18660 points

    Thank you for contacting TI China E2E forum and choosing our products as part of your solution. Regarding your query, please give us some time to confirm this issue.

  • 0 回复 FRANK1
    TI__Guru 54210 points

    您好，

        建议监测一下VCC与PRE，CLR的波形，您的问题与VCC脚在超过1.65V时，PRE CLR的电平不稳定相关。

    xc t 说：
    Changing the 100nF to 10nF improves it a bit, but it still happens.

    CLR的上拉电阻是多大的？也是100K？

    对于您目前的设计，由于PRE已直接上拉到3.3V，您尝试一下增大CLR脚电容（1uf 或10uf)，使芯片在上电时满足PRE=H，CLR=L，

    然后再满足PRE=H，CLR=H的情况，根据CLK的上升沿输出。

    芯片的输出脚是push-pull.