DP83867IR: DP83867 MDIO Stuck High During Power-Up When Two PHYs Share MDIO/MDC

Hi TI Team,

We are using two DP83867 PHYs with an AM6422 processor. The two DP83867 devices share the same MDIO and MDC bus.

In our current hardware design, we have placed one 2.2 kΩ pull-up resistor on the MDIO line close to each DP83867 PHY. Therefore, there are two 2.2 kΩ pull-up resistors connected to the same MDIO bus.

We observed the following issue:

• During power-up, the Ethernet PHYs sometimes cannot be accessed/communicated with properly.
• When the issue occurs, we measured the MDIO signal and found that MDIO stays continuously HIGH.
• If we remove one of the 2.2 kΩ MDIO pull-up resistors and leave only one 2.2 kΩ pull-up resistor on the shared MDIO bus, the issue disappears and the PHYs can be accessed successfully after every power-up.

Could you please help clarify the following questions?

1. For two DP83867 PHYs sharing the same MDIO/MDC bus, should there be only one MDIO pull-up resistor for the entire bus, rather than one pull-up resistor for each PHY?
2. What is TI's recommended pull-up resistance for MDIO when two DP83867 devices are connected to the same AM6422 MDIO bus?
3. Does the physical placement of the MDIO pull-up resistor matter? Should it be placed close to the AM6422 MDIO pin, close to one of the PHYs, or is the location generally not critical?
4. Since two 2.2 kΩ resistors in parallel result in an effective pull-up resistance of approximately 1.1 kΩ, could this pull-up be too strong for the DP83867/AM6422 MDIO interface?
5. When the failure occurs, MDIO remains HIGH. Could this indicate that the PHY or AM6422 MDIO controller is unable to pull the MDIO line LOW due to the effective pull-up resistance being too low?
6. Are there any specific power-up, reset, strap, or MDIO timing requirements we should check for this configuration?

Thanks for your support.