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MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. RMII MODE: Unused in RMII Slave mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. For RMII Master mode, the device outputs the internally generated 50 MHz reference clock on this pin. This pin provides an integrated 50 ohm signal termination, making external termination resistors unnecessary.
TX_CLK: output pin.
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. The MAC should source TX_EN and TXD[3:0] using this clock. RMII MODE: Unused in RMII Slave mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. For RMII Master mode, the device outputs the internally generated 50 MHz reference clock on this pin. This pin provides an integrated 50 ohm signal termination, making external termination resistors unnecessary.
Clk_out
CLOCK OUTPUT: This pin provides a highly configurable system clock, which may have one of four sources: 1. Relative to the internal PTP clock, with a default frequency of 25 MHz (default) 2. 50 MHz RMII reference clock in RMII Master Mode 3. 25 MHz Receive Clock (same as RX_CLK) in 100 Mb mode 4. 25 MHz or 50 MHz pass-through of X1 reference clock CLOCK INPUT: This pin is used to input an external IEEE 1588 reference clock for use by the IEEE 1588 logic. The CLK_OUT_EN strap should be disabled in the system to prevent possible contention. The PTP_CLKSRC register must be configured prior to enabling the IEEE 1588 function in order to allow correct operation.
