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DP83867IS MDIO 一直为低,无法正常驱动

Other Parts Discussed in Thread: DP83867IS

以1M频率的来配置DP83867IS, 由FPGA产生MDC和MDIO, PHY的MDC管脚上能接收正常的1M时钟信号,MDIO(FPGA已产生此信号)无法驱动PHY的MDIO管脚,MDIO当前采用外部2K电阻上拉,但是MDIO一直保持低电平状态,请问该如何解决?多谢。