TLK1521工作一段时间后失去锁定

Hi Anner,

你完成同步的工作方式不好，易出问题。数据手册有介绍两种同步的方式。参考一下：

rapid synchronization
The serializer has the capability to send specific SYNC patterns consisting of nine ones and nine zeros,
switching at the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to the
serializer signal within a deterministic time frame. The transmission of SYNC patterns is selected via the SYNC
input on the serializer. Upon receiving a valid SYNC pulse (wider than 6 clock cycles), 1024 cycles of SYNC
pattern are sent.
When the deserializer detects edge transitions at the serial input, it attempts to lock to the embedded clock
information. The deserializer LOCKB output remains inactive while its clock/data recovery (CDR) locks to the
incoming data or SYNC patterns present on the serial input. When the deserializer locks to the serial data, the
LOCKB output goes active. When LOCKB is active, the deserializer outputs represent incoming serial data. One
approach is to tie the deserializer LOCKB output directly to the SYNC input of the transmitter. This assures that
enough SYNC patterns are sent to achieve deserializer lock.
random lock synchronization
The deserializer can attain lock to a data stream without requiring the serializer to send special SYNC patterns.
This allows the TLK1521 to operate in open-loop applications. Equally important is the deserializer’s ability to
support hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the data
stream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exact
lock time cannot be predicted. The primary constraint on the random lock time is the initial phase relation
between the incoming data and the GTX_CLK when the deserializer powers up.

The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer
could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive
multitransition (RMT). This occurs when more than one low-high transition takes place per clock cycle over
multiple clock cycles. In the worst case, the deserializer could become locked to the data pattern rather than
the clock. Circuitry within the deserializer can detect that the possibility of false lock exists. Upon detection, the
circuitry prevents the LOCKB from becoming active until the potential false-lock pattern changes. Notice that
the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does
not affect the deserializer state as long as the same data boundary happens each cycle. The deserializer does
not go into lock until it finds a unique data boundary that consists of four consecutive start/stop bits at the same
position.
The deserializer stays in lock until it cannot detect the same data boundary (start/stop bits) for four consecutive
cycles. Then the deserializer goes out of lock and hunts for the new data boundary (start/stop bits). In the event
of loss of synchronization, the LOCKB pin output goes inactive and the outputs (including RX_CLK) enter a
high-impedance state. The user’s system should monitor the LOCKB pin in order to detect a loss of
synchronization. Upon detection of loss of lock, sending SYNC patterns for resynchronization is desirable if
reestablishing lock within a specific time is critical. However, the deserializer can lock to random