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开发板上的S5[2] = ON (default)， 默认的是GPIO0和MCU连接的，所以可以通过MCU来控制GPIO0的高低电平。
而SYNC_SW BIT 是通过寄存器配置的，不是引脚来控制的，Table 8 的意思是将SYNC_SW BIT由1配置为0.
而CHx_SYNC_EN bit 这个也是通过寄存器配置的， 根据Table8 上面的描述，可知，将此bit配置为0 并不会影响sync本身这个事件： Output channels with their sync disabled (CHx_SYNC_EN bit = 0) will not be affected by a SYNC event and will continue normal output operation as configured.
但是单纯的通过配置寄存器SYNC_SW 或者通过多路复用引脚GPIO0/Sync 来使能同步的话，就会导致输出mute：
A SYNC event can be asserted by the hardware GPIO0/SYNCN pin (active low) or the SYNC_SW register bit
(active high). When SYNC is asserted, the SYNC-enabled dividers held are reset and clock outputs are muted
选择同步后，输出静音mute了，这是怎么回事？
