问题描述:DP83867IRRGZ 实现100M通信时,PHY与PC端自协商成功,但是PC无法ping通设备的IP地址
硬件平台是Xilinx的ZYNQ7000系列的7020,将DP83867IRRGZ(48pin)与7020的PS端连接,需要在只支持RGMII模式下实现100MHz的网络通信
原理图如下:
strap pin只有38引脚的RX_CTRL上拉5.76K电阻,下拉2.49K电阻,实现mode3 自动协商使能,其他strap pin处于上下拉都open的mode1
通过MDC和MDIO能够正常读写寄存器,寄存器设置如下:
Read Register RegisterNum[0000] PhyData[1140]
Read Register RegisterNum[0001] PhyData[796D]
Read Register RegisterNum[0002] PhyData[2000]
Read Register RegisterNum[0003] PhyData[A231]
Read Register RegisterNum[0004] PhyData[0DE1]
Read Register RegisterNum[0005] PhyData[CDE1]
Read Register RegisterNum[0006] PhyData[006F]
Read Register RegisterNum[0007] PhyData[2001]
Read Register RegisterNum[0008] PhyData[6001]
Read Register RegisterNum[0009] PhyData[0300]
Read Register RegisterNum[000A] PhyData[0800]
Read Register RegisterNum[000B] PhyData[0000]
Read Register RegisterNum[000C] PhyData[0000]
Read Register RegisterNum[000D] PhyData[401F]
Read Register RegisterNum[000E] PhyData[00D3]
Read Register RegisterNum[000F] PhyData[3000]
Read Register RegisterNum[0010] PhyData[1140]
Read Register RegisterNum[0011] PhyData[6C02]
Read Register RegisterNum[0012] PhyData[0000]
Read Register RegisterNum[0013] PhyData[9CC0]
Read Register RegisterNum[0014] PhyData[29C7]
Read Register RegisterNum[0015] PhyData[0000]
Read Register RegisterNum[0016] PhyData[0000]
Read Register RegisterNum[0017] PhyData[0040]
Read Register RegisterNum[0018] PhyData[6150]
Read Register RegisterNum[0019] PhyData[4444]
Read Register RegisterNum[001A] PhyData[0002]
Read Register RegisterNum[001B] PhyData[0000]
Read Register RegisterNum[001C] PhyData[0000]
Read Register RegisterNum[001D] PhyData[0000]
Read Register RegisterNum[001E] PhyData[0002]
Read Register RegisterNum[001F] PhyData[0000]
Read Extended Register RegisterNum[0031] PhyData[10B0]
Read Extended Register RegisterNum[0032] PhyData[00D0]
Read Extended Register RegisterNum[0033] PhyData[0000]
Read Extended Register RegisterNum[0043] PhyData[07A0]
Read Extended Register RegisterNum[0055] PhyData[0000]
Read Extended Register RegisterNum[006E] PhyData[000E]
Read Extended Register RegisterNum[006F] PhyData[0100]
Read Extended Register RegisterNum[0071] PhyData[0000]
Read Extended Register RegisterNum[0072] PhyData[0000]
Read Extended Register RegisterNum[0086] PhyData[00A8]
Read Extended Register RegisterNum[00E9] PhyData[9F22]
Read Extended Register RegisterNum[00FE] PhyData[E721]
调试结果:
1、LED0常亮,表示link建立;LED2间歇闪烁,说明有接收或发送数据
2、可以在连接的PC端通过任务管理器的“联网”看到PC能够发现与100MHz的网络设备的连接,说明PHY与link partner能够协商成功
3、RX_CLK一直输出25MHz的时钟信号,RX_CTRL会间歇产生8321ns左右的高电平,其他时间为低电平,RD0~RD3也能够测量到波形,
但是GTX_CLK一直没有信号产生,TX_CTRL和TX0~TX3也一直保持某一种电平状态,在手册里有这样一段描述,如下图下划线部分,
MAC会将TX_CLK一直保持在低电平,知道确认与PHY同速率。现在的状态GTX_CLK一直没有时钟信号,
是否说明MAC一直没有和PHY同速率?为什么没有同速率?怎样才可以同速率?
综上总结,从现象看,PHY与link partner端的协商正常,但与MAC似乎没有建立起有效的连接。因为对802.3的协议不熟悉,MAC和PHY
之间应该是怎样的数据帧?如何实现这两层的通信?请教各位,以上有哪里是存在问题的点