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使用100M的时钟，100鉴相频率，输出整数点比如1140MHz时信号很好，当输出1140.001MHz时,信号两边会产生很多20k整数倍的杂散信号，最近也是最差的只有23dBc。降低鉴相频率杂散会有所改善，
非常感谢你的回复，今天搞定了，小数模块选择上的问题。
