10s的话没问题，能使得RST为低电平的两个原因：
RSTn is asserted (LOW) for either one of the following conditions:
1. If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately 20 ms).
2. At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising edge (see Figure 8)
所以，电路中我看到 DELAY/M_RST 这个引脚一直拉低的对吧？排除它对RST的影响。
其次就是第二点，电路中， done信号悬空接的吗？最好也检查下焊接情况。
最后，就是您这里提到上电就拉高，事实上，RST拉高也是需要等VDD上电起来稳定之后，至少需要ttR_EXT + tRSTn的时间，请参考Figure
1的时序：
