DS90UB941AS-Q1: 941使用内部clk patgen ，panel没有显示

jianlin fu

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: ALP, USB2ANY

Hi Ti supporter，

硬件连路：fpga dsi0 -> 941 dsi0 -> DOUT0 、DOUT1 -> 2路948 panle，

fpga dsi1 -> 941 dsi0 -> DOUT0 、DOUT1 -> 2路948 panle，

下图是一路941电路图。

目前还在调试941-〉948通路阶段，设置941 patgen 输出color bar video数据到948，

941 patgen采用内部clk，发现948 无法lock pll clock （0x3c[0] 为0），测量948 LOCK pin电平为0.7v

屏没有显示。

附件是941 、948 reg dump 和 init code，请帮忙检查下哪里设置有问题。

enable941pat.txt

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    //config vido
    //941 dsi input config(Single-DSI mode,Select DSI Input port 0,4 Lanes)
    TiSerdes_I2C_Write_Mask(ti941_addr, 0x4F, 0x0C, 0x6C);
    //941 Dual FPD-Link III mode (Single, Dual, or Replicate)
    TiSerdes_I2C_Write_Mask(ti941_addr, 0x5B, 0x3, 0x07);
    TiSerdes_I2C_Write(ti941_addr, 0x17, 0x9e);
    
    //config video
    //948 Dual link based on received data
    TiSerdes_I2C_Write_Mask(ti948_addr, 0x34, 0x8, 0x18);
    //948 Dual FPD/OLDI output
    TiSerdes_I2C_Write_Mask(ti948_addr, 0x49, 0, 0x03);
    //config backlight
    //enable 948 bl pin
    TiSerdes_I2C_Write(ti948_addr, 0x1f, 0x09);
//pg
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    //config vido
    //941 dsi input config(Single-DSI mode,Select DSI Input port 0,4 Lanes)
    TiSerdes_I2C_Write_Mask(ti941_addr, 0x4F, 0x0C, 0x6C);
    //941 Dual FPD-Link III mode (Single, Dual, or Replicate)
    TiSerdes_I2C_Write_Mask(ti941_addr, 0x5B, 0x3, 0x07);

    TiSerdes_I2C_Write(ti941_addr, 0x17, 0x9e);
	
    //config video
    //948 Dual link based on received data
    TiSerdes_I2C_Write_Mask(ti948_addr, 0x34, 0x8, 0x18);
    //948 Dual FPD/OLDI output
    TiSerdes_I2C_Write_Mask(ti948_addr, 0x49, 0, 0x03);

    //config backlight
    //enable 948 bl pin
    TiSerdes_I2C_Write(ti948_addr, 0x1f, 0x09);

//pg
    dm_i2c_reg_write(ti941_addr, 0x66, 0x03);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x02);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x04);
    dm_i2c_reg_write(ti941_addr, 0x67, 0xf8);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x05);
    dm_i2c_reg_write(ti941_addr, 0x67, 0xe7);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x06);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x33);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x07);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x80);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x08);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x07);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x09);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x2d);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0A);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x28);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0B);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x0a);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0C);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x28);
    dm_i2c_reg_write(ti941_addr, 0x66, 0x0D);
    dm_i2c_reg_write(ti941_addr, 0x67, 0x32);

    dm_i2c_reg_write(ti941_addr, 0x65, 0x04);//0x0c selsct dsi clk
    dm_i2c_reg_write(ti941_addr, 0x64, 0x35);

    dm_i2c_reg_write(ti941_addr, 0x17, 0x9e);


//941
18 00 00 9a 00 00 58 00 00 01 4c 02 03 30 00 00 
00 00 00 8f 00 00 fe 9e 7f 7f 01 00 00 00 01 00 
0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a 
00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02 
10 90 00 00 00 00 00 00 00 00 00 00 00 00 00 8c 
16 00 00 00 02 10 00 02 00 00 12 03 07 06 44 00 
22 02 00 00 35 04 0d 32 00 00 00 00 00 00 20 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 7e 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00 
5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 
//948
58 04 00 f0 fe 9e 00 18 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 01 00 00 32 13 53 09 
05 00 40 30 08 00 83 84 21 00 00 00 00 00 00 00 
00 00 90 25 09 00 00 ac 00 00 00 17 20 e0 23 00 
43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00 
03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00 
00 00 00 00 10 00 00 00 00 00 00 00 00 00 01 00 
00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00

3 年多前

0 Kailyn Chen 3 年多前

TI__Guru**** 295050 points

您好， Panel的一些信息可以提供一下。然后参考这篇应用手册中的4.Configuration examples的配置顺序。

https://www.ti.com/lit/an/snla132g/snla132g.pdf

如果使用ALP软件的话，对于pattern generation的配置也相对比较简单，或者如果有USB2ANY板子，通过I2C 连接上941的板子，然后使用USB cable接到PC，使用EVM GUI来对寄存器进行配置和检查。

如果需要我们这边检查寄存器的配置，需要您提供panel的以下信息：

Htotal =

Hactive =

HFP =

HSYNC =

HBP =

Vtotal =

Vactive =

VFP =

VSYNC =

VBP =

0 jianlin fu 3 年多前回复 Kailyn Chen

COG-VLBJT024-01 (BOE 文件编号 CS3-SPM- S065_AV123Z7M-N14-2WP0) 12.3 FHD ADS module Product Specification_Rev.1.pdf

panel信息见附件,ALP软件是指什么?目前是在我司硬件环境上验证,同样的video timing 948 patgen是能点亮屏幕,

但是941->948 由941 patgen没有显示.

0 Kailyn Chen 3 年多前回复 jianlin fu

TI__Guru**** 295050 points

ALP软件参考：

https://www.ti.com.cn/tool/cn/ALP?keyMatch=&tisearch=search-everything&usecase=software

0 jianlin fu 3 年多前回复 Kailyn Chen

941使用内部clk patgen , 948 single link，已经有显示。

然后，修改reg 0x65 = 0xc，也有显示，这时是选择外部dsi clk吗。

但是，再配置reg 0x56 =0x00，选择dsi ref clk，这时就没有显示了。

0 jianlin fu 3 年多前回复 jianlin fu

没显示时，寄存器显示941没有检测到有效pclk， 948也没lock，

请问使用dsi clk，需要注意什么？谢谢

34 00 00 9a 00 00 58 00 00 01 63 03 03 30 00 00
00 00 00 8f 00 00 fe 9e 7f 7f 01 00 00 00 01 00
03 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a
00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02
10 90 00 00 00 00 00 00 00 00 00 00 00 00 00 8c
16 00 00 00 02 10 00 02 00 00 92 01 07 06 44 00
22 02 00 00 31 0c 0d 32 00 00 00 00 00 00 20 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 82 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00
5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00
//948
58 04 00 f0 fe 9e 00 34 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 01 00 00 22 13 53 09
05 00 40 30 00 00 83 84 21 00 00 00 00 00 00 00
00 00 90 25 11 00 00 ac 00 00 00 07 20 e0 23 00
43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00
03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00
00 00 00 00 10 00 00 00 00 00 00 00 00 00 01 00
00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00

+1 Kailyn Chen 3 年多前回复 jianlin fu

TI__Guru**** 295050 points

您好，0x65 bit3=1 即为内部产生patter的外部时钟源。

0x56 如果需要配置的话，使用外部参考时钟应该配置为0x01.

0 jianlin fu 3 年多前回复 Kailyn Chen

谢谢支持.

0 Kailyn Chen 3 年多前回复 jianlin fu

TI__Guru**** 295050 points

不必客气。后续有什么问题，继续讨论。

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DS90UB941AS-Q1: 941使用内部clk patgen ，panel没有显示