I read paper "CDCE72010 Phase Noise Performance and Jitter Cleaning Ability" and use "Passive Loop Filter Circuit" and "CDCE72010 Device Configuration" on this paper, calculate them with "CDCE72010_PLL_Calculation_V1.08.xls",then I find the "phase margin" and "gain peaking" of the filter is not satisfied.Can you explain it for me? Thanks!
