According to document ‘snla246a.pdf’ below configuration, keep FPGA and PC PHY Ethernet cable connection, after setting all analog loopback needed step, then I wait for PHY link status up.
1. Write register 0x001F to 0x8000 to apply a software reset.
2. Write register 0x0000 to 0x0140 to force 1000BASE-T operation.
3. Write register 0x0032 to 0x00D3 to enable RGMII.
4. Write register 0x0016 to 0x0004 to enable digital loopback.
5. Write register 0x001F to 0x4000 to apply a software restart.
If I do not wait for PHY link status up, directly send data and wait for receiving data, I receive nothing.
if I always loop analog loopback configuration then wait for PHY link status up operation, I found that there is a certain possibility of link status is down.
My question is:
(1) If analog loopback must wait for PHY link status up, then send and receive will be ok. If don’t wait, link status is down, it will receive nothing?
(2) What is dependent by link status up, why there is a certain probability of failure for link status?
(3) If analog loopback must wait link status up, how to ensure link status is always up?
Looking forward to reply from TI, thanks in advance.
