DS90UB941AS-Q1: DS90UB941AS-Q1

941 configure：

i2cset -f -y 1 0x0c 0x01 0x08 b
i2cset -f -y 1 0x0c 0x66 0x1A b
i2cset -f -y 1 0x0c 0x67 0x09 b
i2cset -f -y 1 0x0c 0x66 0x03 b
i2cset -f -y 1 0x0c 0x67 0x50 b
i2cset -f -y 1 0x0c 0x66 0x04 b
i2cset -f -y 1 0x0c 0x67 0x10 b
i2cset -f -y 1 0x0c 0x66 0x05 b
i2cset -f -y 1 0x0c 0x67 0x88 b
i2cset -f -y 1 0x0c 0x66 0x06 b
i2cset -f -y 1 0x0c 0x67 0x2F b
i2cset -f -y 1 0x0c 0x66 0x07 b
i2cset -f -y 1 0x0c 0x67 0x80 b
i2cset -f -y 1 0x0c 0x66 0x08 b
i2cset -f -y 1 0x0c 0x67 0x07 b
i2cset -f -y 1 0x0c 0x66 0x09 b
i2cset -f -y 1 0x0c 0x67 0x2D b
i2cset -f -y 1 0x0c 0x66 0x0A b
i2cset -f -y 1 0x0c 0x67 0x0C b
i2cset -f -y 1 0x0c 0x66 0x0B b
i2cset -f -y 1 0x0c 0x67 0x03 b
i2cset -f -y 1 0x0c 0x66 0x0C b
i2cset -f -y 1 0x0c 0x67 0x20 b
i2cset -f -y 1 0x0c 0x66 0x0D b
i2cset -f -y 1 0x0c 0x67 0x18 b
i2cset -f -y 1 0x0c 0x65 0x04 b
i2cset -f -y 1 0x0c 0x64 0x25 b
i2cset -f -y 1 0x0c 0x01 0x00 b

SOC DSI configure：
分辨率：1920x1080
Hsync：118
Hback：200
Hfront：4

Vsync：2
Vback：100
Vfront：38
framerate：60fps

dsi clk: 984M/2 = 498M (dsi输入clk正负均为498M)

Hi,

We're looking into this and please allow some time for us to get back to you.

Thanks

Hi,

Can you see the same flicker with PATGEN?

Have you followed the DSI Bring up guide?

Thanks

We have exported the reference configuration for the 941 development board. The SOC side also uses this version of configuration for initialization. Fortunately, the screen is currently on, but we have discovered a new issue. After the SOC wakes up from sleep, the display screen will flash, which is an inevitable phenomenon. Please help confirm if there is still a problem with the configuration parameters.

The two 941 I2C parameters from the dump are as follows：

Hi，

Will look into it and get back to you soon.

Thanks

Hello, is there any progress in the analysis

Hi,

Can you provide a full register dump file before and after the flicker? Since you only provided the main page of the 941 I also want to see the indirect pages for both devices.

Is this also happening with PATGEN enabled?

Thanks

Hi，How to read the value of an indirect register? Currently, SOC can only dump the value to the main register

Hi,

There are instruction on how to read indirect pages at the beginning of each indirect pages in the 941AS.

• DSI Port 0 and Port 1 Indirect Page
  • Read page 108 in the datasheet.
• Analog Indirect Registers
  • Read page 122 in the datasheet
• Port 0  and Port 1 Pattern Generator Indirect Registers
  • Read page 124 in the datasheet

I also want to take a look at the 948 main page register dumps before and after the flicker.

Can you confirm what is the setup you are using? STP or COAX?

• Based on the register dumps it seems that register 0x5B reads STP mode but I am not sure if they are overriding this bit.
• Share the 941AS schematic as well.

Thanks

It's STP，

This is the register configuration before(SOC sleep) and after(SOC wake up) flashing 

indirect pages:

Direct register:

941 as schematic is this right?

Hi,

We're checking this with our expert, please expect the response by next business day.

Thanks

Hi,

I noticed that the register 0xA, and 0xB in the 941AS register dumps show that CRC errors are maxing out.

• 0xA -- 0xFF
• 0xB -- 0xFF

In 941AS, can you clear them and keep reading these registers in order to see if CRC errors are incrementing again.

1. Set register 0x4[5] to 1 (This will clear the CRC errors)
2. Set register 0x4[5] to 0 (This will set the CRC counter to normal operation)
3. Read multiple times to check if CRC errors increment.

Can you provide the following information:

1. Does that flicker occur only once after waking up the display? Does it occur multiple times?
2. Does that same flicker occur with PATGEN?
   1. This will allow us to know where I should focus either the 941AS or 948
3. Can you read the DSI indirect page again?
   1. Normal file shows DSI errors but black screen file shows no DSI errors.
   2. Please ask to read multiple times.
4. Provide the 941AS schematic.

Thanks

We found that the lock signal of 948 will be pulled down and then raised when the flashing occurs,But the DSI signal is continuous and there are no abnormalities

Hi,

Thank you for the information and because of the Thanksgiving holiday in the U.S, please expect a delayed response from our experts and sorry for any inconvenience.

Thanks

Hi,

It seems Back Channel CRC Errors are incrementing after being cleared. I think that the excessive amount of Back Channel CRC errors are causing the LOCK to be LOW and that is why we see the flicker at the beginning.

Which option best describes how you are powering on the FPD-Link system?

Option #1

1. 941AS powered ON
2. 948 powered ON

Option #2

1. 948 powered ON
2. 941AS powered ON

Could you provide the power sequence for each device:

1. 941AS power sequence
2. 948 power sequence

Finally, are you seeing the same flicker with PATGEN enabled?  

Thanks

Hi,

At present, we should power on the 948 first.  And during SOC sleep, DSI will stop outputting, and 941 and 948 will not power down.It is option #2

941 power sequence:

FPDLINK_A_VDD18

FPDLINK_A_VDDIO

FPDLINK_A_VDD11_P

FPDLINK_A_VDD11

FPDLINK_A_VDD11_L

Simultaneously powered on

948 power sequence:

3.3V enable=====5ms=====1.2V enable=====5ms======1.2V power good=========1.47ms========LOCK detect

I have four questions:

1.What is the correct power-on timing for 941 and 948?

2.What is the reason for CRC errors?

3.How many *** CRC errors will cause a lock down?

4.How can we fix it?

We use the SM8475-EVM -941EVM - display， ALP monitoring. After SM8475 sleeps, the 948link status will drop, and FPDLINK0 and FPDLINK1 will generate errors every time they wake up

When DSI is connected, repeatedly activate the color bar mode without flashing screen

Add: The number of errors has not increased

Hi,

For the ALP video, I am not sure what is happening? I see that there is link drop but are you waking up and off the FPD-Link devices? Or is the flickering happening when the 948 link status drops? Can you confirm that the flicker screen only occurs 1 time and it is 100% failure rate after each wake up? Or does the flicker occur multiple times?

Next action Item:

1. Please turn off the Back Channel in the UB948 by disabling register 0x1[2]. Please note this has to be done locally in the 948.

a. Procedure

• Wake up the FPD-Link system
• We are expecting the display to create a flicker
• SET 0x03[3] = 0
• SET 0x5[7] = 0
• SET 0x1[2] = 0
• Clear BC CRC errors
• Put system in sleep mode (Make sure BC is still disabled)
• Does flicker screen still occur? Let me know if you still sees the flicker.

Also, what is the type of cable that you are using?

Thanks

After SOC sleep, 941 and 948 will link down and only flash once after waking up. This phenomenon is not 100% reproducible and occasionally flashes.

we will turn off the Back Channel in the UB948 by disabling register 0x1[2]，it will be done at 11/27

we usb stp with two fpdlinkIII channel

Hi,

Please keep us updated once you got more details by disabling register 0x1[2].

Thanks

We attempted to set register 0x1 [2]=0, 0x3 [3]=0, 0x5 [7]=0, but 948 was unable to connect. After restarting 948, the display screen returned to normal, but the link status was false, and there were still CRC errors. After SOC sleep, the screen could not light up, and 948 register configuration could not be read through 941. Only by restarting 948 can the screen be lit up.

Hi,

Thank you for the feedback and please feel free to give any information regarding your tests.

Thanks