It will be used in PCIe 5.0 CLOCK design, which can meet PCIE 5.0 delay time (what's the delay time in the 1:2 or 2:1 design?) and phase jitter needs?
It will be used in PCIe 5.0 CLOCK design, which can meet PCIE 5.0 delay time (what's the delay time in the 1:2 or 2:1 design?) and phase jitter needs?
