Hi,TI team:
规格书的推荐设计是10k上拉+10uF到GND;我们当前的设计是使用一个10k下拉+0.01uF电容接到GND,PDB引脚接到MCU,PDB引脚默认拉低,9702的上电时序由MCU控制,9702的1.8V和1.1V上电,然后MCU再拉高PDB引脚。请问,我们的设计是否有问题?
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Hi,TI team:
规格书的推荐设计是10k上拉+10uF到GND;我们当前的设计是使用一个10k下拉+0.01uF电容接到GND,PDB引脚接到MCU,PDB引脚默认拉低,9702的上电时序由MCU控制,9702的1.8V和1.1V上电,然后MCU再拉高PDB引脚。请问,我们的设计是否有问题?