dear:
we use the SN65DP159 for FPGA EVB,we want to 135MHz output!
and setting reg. as picture( flow the datasheet) but the result of refclk_out is 280MHz
how can we set the reg. to get 135MHz ?or should we set the others reg.?
thanks
Hi,
The clock output, available only in 48-pin version of DP159, is a divided down (datarate/20 or datarate/40) version of the clock feeding the OUT[3:0]P/N. For example for a 5.4 Gbps (HBR2) datarate, the clock output can be either 135 MHz (divide by 40) or 270 MHz (divide by 20). So what is the datarate at the DP159 input, is it 2.7Gbps or 5.4Gbps?
Thanks
Hi,
In the DP159 init code, are you writing 0xC0 to register 0x0D?
This will be page 0.