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器件型号：AM263P4-Q1 主题中讨论的其他器件：TMDSCNCD263P、 UNIFLASH
工具与软件：
您好！
我们的 TMDSCNCD263P 板将位于高压环境中的外壳中。 因此、我们无法轻松到达电路板并更改引导模式。
没错、此处的说明(AM263Px MCU+ SDK：TI Uniflash 工具)中提到了将器件置于 DevBoot 模式。 不过、在实践中、我已经能够使用板载 XDS110调试仿真器以 QSPI (1S)模式进行刷写几个月、直到最近为止、无论使用 DevBoot 的指令是什么。 因此、我从未担心需要更改引导模式开关。
我的问题是、现在由于某种原因、它现在失败了、如下所示：
[10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched*** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait... [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000002 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: QSPI - 1S Functional boot mode [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000101 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Lockstep mode [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual core mode [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 Reset DualCore *** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: ***R5FSS1 Reset DualCore *** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: *********** R5FSS0/1 Dual Core mode Configured******** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2 [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks *** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling QSPI Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled*** [10/02/2025, 17:13:12] [INFO] Cortex_R5_0: Writing Flash @ Address 0x60000000 of Length 0x00007ff0 [10/02/2025, 17:13:33] [ERROR] Cortex_R5_0: Run failed... [10/02/2025, 17:13:33] [ERROR] Cortex_R5_0: File Loader: Memory write failed: Timed out waiting for target to halt while executing am263px_flasher.out
正如您在日志中看到的、UniFlash 在连接到器件时没有问题。 我已将 UNIFLASH 8.7尝试到9.0、
我希望您能理解、必须从 QSPI (1S)-> DevBoot -> QSPI (1S)更改引导模式对我们来说完全不切实际。
我的第一个请求：请告知为什么(原则上) SOC 无法在 QSPI (1S) 模式下进行刷写。 这可能提供了一些线索,我如何才能挽救情况。
