Other Parts Discussed in Thread: SYSCONFIG
器件型号: TMDSCNCD263P
主题: SysConfig 中讨论的其他器件
为 AM263Px 运行 MCU+ SDK 的 DCC 示例失败。
我以前使用过
- AM263Px 控制卡
- SysConfig 1.25.0
- 适用于 AM263Px 11.0.0.19 的 MCU+ SDK
- CCS 20.3.1.5___1.9.1
首先、我执行了 SOC 初始化、使用 OSPI 存储器中刷写的二进制文件 来设置 EVM。
刷写 SBL_null 并将 EVM 引导模式切换到 OSPI 后、我 在 R5FSS0 内核 0 上运行了 SDL DCC 示例。
Usecase 3 失败、因为接收到如下日志所示的意外错误中断。
Cortex_R5_0: DCC Example Test Application
Cortex_R5_0:
Cortex_R5_0: DCC_Test_init: Init ESM complete
Cortex_R5_0:
Cortex_R5_0: USECASE: 0
Cortex_R5_0: Source clock: XTAL_CLK
Cortex_R5_0: Test clock: RCCLK32K
SDL DCC EXAMPLE TEST: Warning Seed value for valid count exceeds allowed range.
SDL DCC EXAMPLE TEST: Application will run with 0 allowed drift.
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
Cortex_R5_0: UC-0 Completed Successfully
Cortex_R5_0:
Cortex_R5_0: USECASE: 1
Cortex_R5_0: Source clock: XTAL_CLK
Cortex_R5_0: Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
Cortex_R5_0: UC-1 Completed Successfully
Cortex_R5_0:
Cortex_R5_0: USECASE: 2
Cortex_R5_0: Source clock: XTAL_CLK
Cortex_R5_0: Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time
Cortex_R5_0: UC-2 Completed Successfully
Cortex_R5_0:
Cortex_R5_0: USECASE: 3
Cortex_R5_0: Source clock: RCCLK10M
Cortex_R5_0: Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Error : DCC Generated error interrupt
SDL DCC EXAMPLE TEST: Error interrupt is not expected
Cortex_R5_0: UC-3 Failed
Cortex_R5_0:
Cortex_R5_0: Few/all tests Failed







