Other Parts Discussed in Thread: AM2612
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器件型号： AM2612
您好！
我目前正在尝试在带有 TI AM2612 芯片的定制硬件上将 IS66WV032 PSRAM 与 OSP1 外设集成。
主要问题是 PHY 模式和 DQS 信号来正确地对输入数据进行采样。 只要未启用 PHY 模式、我就会获得地址和虚拟所需的 CLK 周期、直到数据被采样。 据我所知、如果禁用 PHY 模式、OSP1 外设是否会在 SCLK 周期内对数据进行采样。 只有启用 PHY 模式时、DQS 信号才用于对数据进行采样。
如果我启用 PHY 模式、我将只获得一个 SCLK 周期、这个周期当然不足以触发地址、还会得到必要的虚拟周期、直到提供 DQS 信号。
正确配置 PHY 模式需要满足哪些条件？
相关的 PHY 配置（省略地址和虚拟周期的配置，这些周期似乎适用于禁用的 PHY）：
/* Select the number of delay element to be inserted between
* phase detect flip-flops.
*/
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_MASTER_CONTROL_REG,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,
2U);
/* Configure PHY in Master operational mode */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_MASTER_CONTROL_REG,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_BYPASS_MODE_FLD,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_MODE);
/* Set the read delay */
CSL_REG32_FINS(&ospi1_flash_cfg->RD_DATA_CAPTURE_REG,
OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_DELAY_FLD,
5);
/* Sampled on rising edge of clock */
CSL_REG32_FINS(&ospi1_flash_cfg->RD_DATA_CAPTURE_REG,
OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD,
CSL_OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD_MAX);
/* Try RX DLL BYPASS ?? */
// CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG, OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_BYPASS_FLD, 1);
/* Set TX DLL delay */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_TX_DLL_DELAY_FLD,
6);
/* Set RX DLL delay */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_DELAY_FLD,
6);
/* phy enable */
CSL_REG32_FINS(&ospi1_flash_cfg->CONFIG_REG, OSPI_FLASH_CFG_CONFIG_REG_PHY_MODE_ENABLE_FLD, TRUE);
uint32_t idleFlag = 0;
/* Wait for Idle */
while (idleFlag == 0)
{
idleFlag = CSL_REG32_FEXT(&ospi1_flash_cfg->CONFIG_REG,
OSPI_FLASH_CFG_CONFIG_REG_IDLE_FLD);
}
/* Disable OSPI Controller */
CSL_REG32_FINS(&ospi1_flash_cfg->CONFIG_REG,
OSPI_FLASH_CFG_CONFIG_REG_ENB_SPI_FLD,
FALSE);
/* Clear the delay line resync bit */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESYNC_FLD,
0U);
/* Reset DLL in master mode */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESET_FLD,
0U);
/* Set Initial delay for the master DLL */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_MASTER_CONTROL_REG,
OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_INITIAL_DELAY_FLD,
0x5U);
/* DLL out of reset */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESET_FLD,
1U);
/* Wait DLL lock done */
while ((CSL_REG32_FEXT(&ospi1_flash_cfg->DLL_OBSERVABLE_LOWER_REG,
OSPI_FLASH_CFG_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD) == 0U))
{
(void)idleFlag;
}
/* Wait DLL loopback lock done */
while ((CSL_REG32_FEXT(&ospi1_flash_cfg->DLL_OBSERVABLE_LOWER_REG,
OSPI_FLASH_CFG_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD) == 0U))
{
(void)idleFlag;
}
/* Resync the Slave DLLs */
CSL_REG32_FINS(&ospi1_flash_cfg->PHY_CONFIGURATION_REG,
OSPI_FLASH_CFG_PHY_CONFIGURATION_REG_PHY_CONFIG_RESYNC_FLD,
1U);
/* enable SPI */
CSL_REG32_FINS(&ospi1_flash_cfg->CONFIG_REG,
OSPI_FLASH_CFG_CONFIG_REG_ENB_SPI_FLD,
1);