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[参考译文] AM263P4：Uniflash CLI 擦除命令

admin
Guru**** 2964790 points

Other Parts Discussed in Thread: UNIFLASH

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1657872/am263p4-uniflash-cli-erase-command

器件型号： AM263P4
Thread 中讨论的其他器件： UNIFLASH

我正在使用 uniflash CLI 对应用程序进行编程。  我希望在编程前执行擦除、以确保未编程的区域中没有旧数据。

我尝试了下面的命令擦除,但它不工作. 从日志中可以看到它返回的操作无效。

-c user_files/configs/AM263Px_ZCZ_F.ccxml -l user_files/settings/generated.ufsettings -e -b 擦除

然后我尝试修改命令 EraseAll 如下所示、可以看到它正常工作。

-c user_files/configs/AM263Px_ZCZ_F.ccxml -l user_files/settings/generated.ufsettings -e -b EraseAll

您能否确认这是用于擦除操作的正确命令？ 我在用户指南中没有看到相关信息。

此致、
Richard

 

  • 0
    TI__Guru**** 2964790 points
    请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

    尊敬的 Richard：

    感谢您的查询。 我正在从我这边检查这个。 我会尽快回到您身边。

    此致、

    Aswin

  • 0
    TI__Guru**** 2964790 points
    请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

    尊敬的 Richard：  

    您是否可以按照以下步骤使用 Uniflash CLI 工具启用擦除

    1.全部擦除： ./dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -b EraseAll

    2.擦除特定块： .\dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -s StandaloneEraseSpecificText=5 -b EraseBlocks

    3.擦除块范围： .\dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -s StandaloneEraseSpecificText=0-10 -b EraseBlocks

    4.擦除混合的块范围： .\dslite-Cortex_R5_0.bat --config=user_files/configs/AM263Px_ZCZ_F.ccxml -s “StandaloneEraseSpecificText=0-5、8“-b EraseBlocks

    如果是全部擦除、则需要以下日志

    Cortex_R5_0: GEL Output: Gel files loading Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. 
Please Wait...


Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present 
Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000B    
Cortex_R5_0: GEL Output: Dev Boot Mode 
Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA    
Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001    
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000    
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode 
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode 
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: r5fss0 = 0x00000001    
Cortex_R5_0: GEL Output: r5fss1 = 0x00000000    
Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode 
Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode 
Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz 
Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
Cortex_R5_0: GEL Output: 

 *** Enabling Peripheral Clocks *** 
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks 
Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks 
Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks 
Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
Cortex_R5_0: GEL Output: Enabling OSPI Clocks 
Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
Cortex_R5_0: GEL Output: Enabling I2C Clocks 
Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling TRACE Clocks 
Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks 
Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks 
Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks 
Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks 
Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
Cortex_R5_0: GEL Output: Enabling CPTS Clocks 
Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks 
Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks 
Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks 
Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
Cortex_R5_0: GEL Output: 

 ***All IP Clocks are Enabled*** 

info: Cortex_R5_0: AM263Px_ZCZ_F
info: Cortex_R5_0: Board Selected : EVM
info: Cortex_R5_0: Part Selected : SIP (On-Chip Flash)
info: Cortex_R5_0: Erasing 1 Block ..
info: Cortex_R5_0: Erasing 2 Block ..
info: Cortex_R5_0: Erasing 3 Block ..
info: Cortex_R5_0: Erasing 4 Block ..
info: Cortex_R5_0: Erasing 5 Block ..
info: Cortex_R5_0: Erasing 6 Block ..
info: Cortex_R5_0: Erasing 7 Block ..
info: Cortex_R5_0: Erasing 8 Block ..
info: Cortex_R5_0: Erasing 9 Block ..
info: Cortex_R5_0: Erasing 10 Block ..
info: Cortex_R5_0: Erasing 11 Block ..
info: Cortex_R5_0: Erasing 12 Block ..
info: Cortex_R5_0: Erasing 13 Block ..
info: Cortex_R5_0: Erasing 14 Block ..
info: Cortex_R5_0: Erasing 15 Block ..
info: Cortex_R5_0: Erasing 16 Block ..
info: Cortex_R5_0: Erasing 17 Block ..
info: Cortex_R5_0: Erasing 18 Block ..
info: Cortex_R5_0: Erasing 19 Block ..
info: Cortex_R5_0: Erasing 20 Block ..
info: Cortex_R5_0: Erasing 21 Block ..
info: Cortex_R5_0: Erasing 22 Block ..
info: Cortex_R5_0: Erasing 23 Block ..
info: Cortex_R5_0: Erasing 24 Block ..
info: Cortex_R5_0: Erasing 25 Block ..
info: Cortex_R5_0: Erasing 26 Block ..
info: Cortex_R5_0: Erasing 27 Block ..
info: Cortex_R5_0: Erasing 28 Block ..
info: Cortex_R5_0: Erasing 29 Block ..
info: Cortex_R5_0: Erasing 30 Block ..
info: Cortex_R5_0: Erasing 31 Block ..
info: Cortex_R5_0: Erasing 32 Block ..
info: Cortex_R5_0: Erasing 33 Block ..
info: Cortex_R5_0: Erasing 34 Block ..
info: Cortex_R5_0: Erasing 35 Block ..
info: Cortex_R5_0: Erasing 36 Block ..
info: Cortex_R5_0: Erasing 37 Block ..
info: Cortex_R5_0: Erasing 38 Block ..
info: Cortex_R5_0: Erasing 39 Block ..
info: Cortex_R5_0: Erasing 40 Block ..
info: Cortex_R5_0: Erasing 41 Block ..
info: Cortex_R5_0: Erasing 42 Block ..
info: Cortex_R5_0: Erasing 43 Block ..
info: Cortex_R5_0: Erasing 44 Block ..
info: Cortex_R5_0: Erasing 45 Block ..
info: Cortex_R5_0: Erasing 46 Block ..
info: Cortex_R5_0: Erasing 47 Block ..
info: Cortex_R5_0: Erasing 48 Block ..
info: Cortex_R5_0: Erasing 49 Block ..
info: Cortex_R5_0: Erasing 50 Block ..
info: Cortex_R5_0: Erasing 51 Block ..
info: Cortex_R5_0: Erasing 52 Block ..
info: Cortex_R5_0: Erasing 53 Block ..
info: Cortex_R5_0: Erasing 54 Block ..
info: Cortex_R5_0: Erasing 55 Block ..
info: Cortex_R5_0: Erasing 56 Block ..
info: Cortex_R5_0: Erasing 57 Block ..
info: Cortex_R5_0: Erasing 58 Block ..
info: Cortex_R5_0: Erasing 59 Block ..
info: Cortex_R5_0: Erasing 60 Block ..
info: Cortex_R5_0: Erasing 61 Block ..
info: Cortex_R5_0: Erasing 62 Block ..
info: Cortex_R5_0: Erasing 63 Block ..
info: Cortex_R5_0: Erasing 64 Block ..

    此致、

    Aswin

  • 0
    TI__Guru**** 2964790 points
    请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

    尊敬的 Aswin：

    上面的命令列表很有用。 感谢您的建议。

    此致、

    Richard