我测量了从_c_int00到我第一次调用 main ()所花费的周期、我获得了超过16ms 的时间、以100MHz 的频率运行内核。 如果这是真的、那么这对我的系统来说是个问题、我需要得到最大7ms 的时间。
我开始测量 -在 PMU 中使用周期计数器-从 errata_PBIST_4()行之后开始 ; (理想情况下,我希望在 PLL 配置和锁定后直接开始,但该勘误方法重置/重新配置 PMU,我懒惰地记录 PMU 前后的周期并进行累加。)
查找/步进块,大部分时间都处于忙状态,等待自检完成, 启动-逐一等待:
* Run PBIST on STC ROM */
pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
* Wait for PBIST for STC ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
....
...
* Run PBIST on PBIST ROM */
pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
/* Wait for PBIST for PBIST ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
.....
/* Run PBIST on CPU RAM.
* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
* device datasheet.
*/
pbistRun(0x00300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);
/* USER CODE BEGIN (32) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
...
// ( OTHER .. )
是否不可能启动尽可能多的正常(按依赖项..?) 一次、然后在结束时等待? 或者提供的代码是否尽可能多地同时启动测试。
如果可以在这里进行任何旋转、该怎么办?