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[参考译文] AM2432：如何将 GPIO 输入中断连接到特定的 R5内核？

admin
Guru**** 2595770 points
Other Parts Discussed in Thread: AM2432, SYSCONFIG

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1164540/am2432-how-to-connect-a-gpio-input-interrupt-to-a-specific-r5-core

器件型号：AM2432
Thread 中讨论的其他器件： SysConfig

系统设置：

AM2432
SDK MCU_PLUS_SDK_am243x_08_04_00_17
SysConfig 1.14
CCS 12.1.0.00007

您好！


我正在尝试设置由主域中引脚 Y1上的引脚 PRG0_PRU0_GPO0 (GPIO1_0)触发的中断。  ISR 必须由 R5FSS1_CORE0提供服务。  当我配置 GPIO 引脚为中断提供服务时、SysConfig 生成了以下文件(ti_drivers_config.c)、其中包含设置中断的代码。  但是，当在 ti_drivers_config.c 中调用 Sciclient_gpioIrqSet()时，对 Sciclient_rmIrqSet()的调用失败。  
随附了我的 example.syscfg 和 ti_drivers_config.c 文件：

e2e.ti.com/.../4747.ti_5F00_drivers_5F00_config.c

示例.syscfg： 

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss1-0" --product "MCU_PLUS_SDK_AM243x@08.04.00"
 * @versions {"tool":"1.14.0+2667"}
 */

/**
 * Import the modules used in this configuration.
 */
const flash      = scripting.addModule("/board/flash/flash", {}, false);
const flash1     = flash.addInstance();
const gpio       = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1      = gpio.addInstance();
const i2c        = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1       = i2c.addInstance();
const i2c2       = i2c.addInstance();
const ipc        = scripting.addModule("/drivers/ipc/ipc");
const mcspi      = scripting.addModule("/drivers/mcspi/mcspi", {}, false);
const mcspi1     = mcspi.addInstance();
const mcspi2     = mcspi.addInstance();
const uart       = scripting.addModule("/drivers/uart/uart", {}, false);
const uart1      = uart.addInstance();
const watchdog   = scripting.addModule("/drivers/watchdog/watchdog", {}, false);
const watchdog1  = watchdog.addInstance();
const clock      = scripting.addModule("/kernel/dpl/clock");
const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
const mpu_armv77 = mpu_armv7.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
flash1.$name                         = "CONFIG_FLASH0";
flash1.peripheralDriver.$name        = "CONFIG_OSPI0";
flash1.peripheralDriver.inputClkFreq = 200000000;
flash1.peripheralDriver.dmaEnable    = true;
flash1.peripheralDriver.advanced     = true;

gpio1.$name                = "GPIO_UPDATE_PS";
gpio1.trigType             = "RISE_EDGE";
gpio1.advanced             = true;
gpio1.intrOut              = "12";
gpio1.GPIO.$assign         = "GPIO1";
gpio1.GPIO.gpioPin.$assign = "ball.Y1";

i2c1.$name           = "CONFIG_I2C0";
i2c1.advanced        = true;
i2c1.I2C.$assign     = "I2C0";
i2c1.I2C.SCL.$assign = "ball.A18";
i2c1.I2C.SDA.$assign = "ball.B18";

i2c2.$name           = "CONFIG_I2C1";
i2c2.advanced        = true;
i2c2.I2C.$assign     = "I2C1";
i2c2.I2C.SCL.$assign = "ball.C18";
i2c2.I2C.SDA.$assign = "ball.B19";

ipc.r5fss0_1     = "NONE";
ipc.r5fss1_1     = "NONE";
ipc.m4fss0_0     = "notify";
ipc.vringMsgSize = 256;
ipc.vringNumBuf  = 12;

mcspi1.$name                         = "CONFIG_MCSPI0";
mcspi1.SPI.$assignAllowConflicts     = "SPI0";
mcspi1.SPI.CLK.$assignAllowConflicts = "ball.D13";
mcspi1.SPI.D0.$assignAllowConflicts  = "ball.A13";
mcspi1.SPI.D1.$assignAllowConflicts  = "ball.A14";
mcspi1.mcspiChannel[0].$name         = "CONFIG_MCSPI_CH0";
mcspi1.mcspiChannel[0].CSn.$assign   = "ball.D12";
scripting.suppress("Resource conflict,SPI0 is also in use by @@@.+?@@@", mcspi1.SPI, "$assign");
scripting.suppress("Resource conflict,@@@.+?@@@ is also in use by @@@.+?@@@", mcspi1.SPI, "CLK");
scripting.suppress("Resource conflict,@@@.+?@@@ is also in use by @@@.+?@@@", mcspi1.SPI, "D0");
scripting.suppress("Resource conflict,@@@.+?@@@ is also in use by @@@.+?@@@", mcspi1.SPI, "D1");

mcspi2.$name                         = "CONFIG_MCSPI1";
mcspi2.SPI.$assignAllowConflicts     = "SPI0";
mcspi2.SPI.CLK.$assignAllowConflicts = "ball.D13";
mcspi2.SPI.D0.$assignAllowConflicts  = "ball.A13";
mcspi2.SPI.D1.$assignAllowConflicts  = "ball.A14";
mcspi2.mcspiChannel[0].$name         = "CONFIG_MCSPI_CH1";
mcspi2.mcspiChannel[0].CSn.$assign   = "ball.C13";
scripting.suppress("Resource conflict,SPI0 is also in use by @@@.+?@@@", mcspi2.SPI, "$assign");
scripting.suppress("Resource conflict,@@@.+?@@@ is also in use by @@@.+?@@@", mcspi2.SPI, "CLK");
scripting.suppress("Resource conflict,@@@.+?@@@ is also in use by @@@.+?@@@", mcspi2.SPI, "D0");
scripting.suppress("Resource conflict,@@@.+?@@@ is also in use by @@@.+?@@@", mcspi2.SPI, "D1");

uart1.$name            = "CONFIG_UART0";
uart1.rxTrigLvl        = "1";
uart1.intrEnable       = "USER_INTR";
uart1.txTrigLvl        = "8";
uart1.UART.$assign     = "USART1";
uart1.UART.RXD.$assign = "ball.E15";
uart1.UART.TXD.$assign = "ball.E14";

const udma                         = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1                        = udma.addInstance({}, false);
udma1.$name                        = "CONFIG_UDMA0";
flash1.peripheralDriver.udmaDriver = udma1;

watchdog1.$name     = "CONFIG_WDT10";
watchdog1.instance  = "WDT10";
watchdog1.resetMode = "Watchdog_RESET_OFF";

debug_log.enableSharedMemLog = true;

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv72.$name             = "CONFIG_MPU_ATCM";

mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv73.$name             = "CONFIG_MPU_BTCM";

mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;
mpu_armv74.$name             = "CONFIG_MPU_MSRAM_ALL";

mpu_armv75.baseAddr = 0xC0000000;
mpu_armv75.size     = 30;
mpu_armv75.$name    = "CONFIG_MPU_DDR";

mpu_armv76.allowExecute = false;
mpu_armv76.size         = 17;
mpu_armv76.attributes   = "NonCached";
mpu_armv76.$name        = "CONFIG_MPU_MSRAM_NOCACHE";
mpu_armv76.baseAddr     = 0x70120000;

mpu_armv77.baseAddr     = 0x701D0000;
mpu_armv77.size         = 16;
mpu_armv77.attributes   = "Device";
mpu_armv77.allowExecute = false;
mpu_armv77.$name        = "CONFIG_MPU_MSRAM_SHARED";

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
flash1.peripheralDriver.OSPI.$suggestSolution      = "OSPI0";
flash1.peripheralDriver.OSPI.CLK.$suggestSolution  = "ball.N20";
flash1.peripheralDriver.OSPI.CSn0.$suggestSolution = "ball.L19";
flash1.peripheralDriver.OSPI.DQS.$suggestSolution  = "ball.N19";
flash1.peripheralDriver.OSPI.D7.$suggestSolution   = "ball.M17";
flash1.peripheralDriver.OSPI.D6.$suggestSolution   = "ball.N18";
flash1.peripheralDriver.OSPI.D5.$suggestSolution   = "ball.P20";
flash1.peripheralDriver.OSPI.D4.$suggestSolution   = "ball.P21";
flash1.peripheralDriver.OSPI.D3.$suggestSolution   = "ball.M21";
flash1.peripheralDriver.OSPI.D2.$suggestSolution   = "ball.M20";
flash1.peripheralDriver.OSPI.D1.$suggestSolution   = "ball.M18";
flash1.peripheralDriver.OSPI.D0.$suggestSolution   = "ball.M19";

根据相关的支持请求、我需要进行修改 sources\drivers\sciclient\sciclient_default_boardcfg\am64x_am243x\sciclient_defaultBoardcfg_rm.c 以完成从中断源到请求内核(R5FSS1_CORE0)的管道。  如何修改该文件以将 GPIO1_0连接到 R5FSS1_CORE0？  是否有描述此过程的文档(AM243x MCU+ SDK 文档的"修改资源分配"部分除外)？  相关的支持请求对于如何执行此操作不是很清楚、我在阅读相关的支持请求单或 SDK 文档时也不清楚"启动资源"和"num_resource"在配置的"资源类型"中指的是什么。

它非常令人困惑。

如果有任何帮助，将不胜感激。

谢谢。

  • 0
    TI__Guru**** 2595770 points
    请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

    您好、Scott、

    [引用 userid="521726" URL"~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1164540/am2432-how-to-connect-a-gpio-input-interrupt-to-a-specific-r5-core "]是否有一个介绍此过程的文档(AM243x MCU+ SDK 文档的"修改资源分配"部分除外)？

    否、目前没有更好地描述此过程的文档。 但是、SDK 08.05中将进行更新、以简化 RM 更改。

    [引用 userid="521726" URL"~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1164540/am2432-how-to-connect-a-gpio-input-interrupt-to-a-specific-r5-core "]相关的支持请求对于如何执行此操作并不是很清楚，我在阅读相关的支持请求单或 SDK 文档时不清楚'start resources'和'num_resources'在配置的'type of resources'中指的是什么。

    您能否查看此常见问题解答是否有帮助？

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1123825/faq-am6442-how-to-configure-the-gpio-interrupt

    此致、
    弗兰克

  • 0
    TI__Guru**** 2595770 points
    请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

    您好、Frank、

    常见问题解答帮助了-我现在看到了资源的定义位置，但是对 Sciclient_rmIrqSet()的调用仍然失败(返回-1)。  我的设置如下：

    用于 ISR 的内核为 R51_Core0、因此 sciclient_defaultBoardcfg_rm.c 中的条目为：

           ｛
               num_resource = 2、
               .type = TISCI_RESSASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0、TISCI_RESSASG_SUBTYPE_IR_OUTPUT)、
               .start_resource = 12、
               .host_id = TISCI_HOST_ID_MAIN_1_R5_1、
           }、

    GPIO 引脚配置如下：

          GPIO1_0 (引脚 Y1)、输入、上升沿、ROUTER12或 ROUTER13。选中启用中断配置复选框后。

    SysConfig 生成以下代码(使用 ROUTER13)： 

    /* This is based on DMSC board config and core */
#define BOARD_BUTTON_GPIO_INTR_NUM     (CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_13)

/*GPIO Interrupt Macros */
#define BOARD_BUTTON_GPIO_SWITCH_NUM    (5)

/** \brief bank interrupt source index base */
#define TISCI_BANK_SRC_IDX_BASE_GPIO0       (90U)
#define TISCI_BANK_SRC_IDX_BASE_GPIO1       (90U)
#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0   (90U)


static void Sciclient_gpioIrqSet(void);
static void Sciclient_gpioIrqRelease(void);


void Board_gpioInit(void)
{
    Sciclient_gpioIrqSet();
}

void Board_gpioDeinit(void)
{
    Sciclient_gpioIrqRelease();
}

uint32_t Board_getGpioButtonIntrNum(void)
{
    return (BOARD_BUTTON_GPIO_INTR_NUM);
}


uint32_t Board_getGpioButtonSwitchNum(void)
{
    return (BOARD_BUTTON_GPIO_SWITCH_NUM);
}

static void Sciclient_gpioIrqSet(void)
{
    int32_t                             retVal;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO1;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(0);
    rmIrqReq.dst_id                 = TISCI_DEV_R5FSS1_CORE0;
    rmIrqReq.dst_host_irq           = CSLR_R5FSS1_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_13;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
    if(0 != retVal)
    {
        DebugP_log("[Error] Sciclient event config failed!!!\r\n");
        DebugP_assert(FALSE);
    }
    return;
}

static void Sciclient_gpioIrqRelease(void)
{
    int32_t                             retVal;
    struct tisci_msg_rm_irq_release_req rmIrqReq;
    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO1;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(0);
    rmIrqReq.dst_id                 = TISCI_DEV_R5FSS1_CORE0;
    rmIrqReq.dst_host_irq           = CSLR_R5FSS1_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_13;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqRelease(&rmIrqReq, SystemP_WAIT_FOREVER);
    if(0 != retVal)
    {
        DebugP_log("[Error] Sciclient event reset failed!!!\r\n");
        DebugP_assert(FALSE);
    }
    return;
}
    ：

    对 Sciclient_rmIrqSet()的调用返回-1。  Sciclient_rmIrqSet()调用树中的函数 Sciclient_rmIrqFindRoute()生成错误。  ROUTER12的故障方式相同。

    这看起来是正确的、还是我错过了什么？

    此致、

    Scott

  • 0
    TI__Guru**** 2595770 points
    请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

    您好、Scott、

    很抱歉耽误你的回答。

    我将看到我是否可以在我的一侧重现这种行为。 我会随时向您发布。

    此致、
    弗兰克

  • 0
    TI__Guru**** 2595770 points
    请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

    您好、Scott、

    我为使用 GPIO1_0 (Y1)的 R51_0创建了一个新示例。

    对于主域 GPIO IR、我看到 IR 输入180 (主 GPIO 组 Int 0)路由到 IR 输出12：

    在默认的 RM 文件(sciclient_defaultBoardcfg_rm.c)中、IR 输出12分配给 R51_Core0、VIM 中断#44。

    我已附加完整的 CCS 项目。 请告诉我这是否有帮助。

    此致、
    弗兰克

    e2e.ti.com/.../gpio_5F00_input_5F00_interrupt_5F00_am243x_2D00_evm_5F00_r5fss1_2D00_0_5F00_nortos_5F00_ti_2D00_arm_2D00_clang.zip