[参考译文] TM4C129ENCPDT：无法接收数据、EK-TM4C129EXL 板中使用 SSI UDMA 基本模式发送的数据

SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN |
                    SYSCTL_USE_PLL | SYSCTL_CFG_VCO_240), 120000000);

    for(i = 0; i < SSI_TXBUF_SIZE; i++)
    {
        // Wait for data to be available in the receive buffer
        while(SSIDataGetNonBlocking(SSI1_BASE, &u32Rxdata[i])) {}
    }

    //print on console
    for(i = 0; i< SSI_TXBUF_SIZE; i++)
    {

        printf("u32Rxdata[%d] = %d\n", i, u32Rxdata[i]);
    }

// uDMA_OLED_transfer.c
// this transfer data from data buffer of uC to OLED display

#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include "inc/hw_memmap.h"
#include "driverlib/sysctl.h"
#include "driverlib/udma.h"
#include "driverlib/pin_map.h"
#include "driverlib/gpio.h"
#include "driverlib/ssi.h"

#define UDMA_TRANSFER_CHANNEL   UDMA_CHANNEL_SSI1TX
#define UDMA_RX_CHANNEL   		UDMA_CHANNEL_SSI1RX
#define SSIDATA_FRAME_SIZE      UDMA_SIZE_8
#define TIMES_DMA_TRANSFER      UDMA_ARB_128
#define UDMA_TRANSFER_MODE      UDMA_MODE_BASIC
#define SSI_TXBUF_SIZE          1024

unsigned char pui8ControlTable[1024];
unsigned char g_ui8TxBuf[SSI_TXBUF_SIZE];

OLED_Init()
{
    SSI_Init();
    ....
}
void init_uDMA()
{
    //called once to configure or initiate uDMA
    printf("uDMA module initiating\n");
    //
    // Enable the UDMA peripheral
    //
    printf("---- Enabling UDMA Peripheral----\n");
    SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);

    //
    // Wait for the UDMA module to be ready.
    //
    printf("---- Waiting for UDMA Peripheral to ready----\n");
    while(!SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)){}
	
    //enabling the uDMA module
    uDMAEnable();

    uDMAControlBaseSet(&pui8ControlTable[0]);

    printf("uDMA channel control base set done\n");
    //
    // Put the attributes in a known state for the uDMA SSI1TX channel.  These
    // should already be disabled by default.
    //
    uDMAChannelAttributeDisable(UDMA_TRANSFER_CHANNEL | ,UDMA_ATTR_ALTSELECT |
                                UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK);

    uDMAChannelAttributeEnable(UDMA_TRANSFER_CHANNEL | , UDMA_ATTR_USEBURST);
    printf("uDMA channel attributes set done\n");


    uDMAChannelControlSet(UDMA_TRANSFER_CHANNEL | UDMA_PRI_SELECT,
                          SSIDATA_FRAME_SIZE | UDMA_SRC_INC_8 |
                          UDMA_DST_INC_NONE | TIMES_DMA_TRANSFER);
    printf("uDMA channel control set is done\n");


    //
    // Enable the uDMA interface for TX channel.
    //
    //
    SSIDMAEnable(SSI1_BASE, SSI_DMA_TX); // transfer the control to uDMA controller
}

void config_DMA_transfer()
{
   printf("SSI1 Transfering\n");
   static uint_fast16_t ui16Idx;

       //
       // Fill the TX buffer with a simple data 0 to 255.
       //
   for(ui16Idx = 0; ui16Idx < SSI_TXBUF_SIZE; ui16Idx++)
       {
           g_ui8TxBuf[ui16Idx] = ui16Idx;
           printf("g_ui8TxBuf %d\n", g_ui8TxBuf[ui16Idx]);
       }

   printf("DMA Transfer enabled\n");
    

   uDMAChannelTransferSet(UDMA_TRANSFER_CHANNEL | UDMA_PRI_SELECT,
                          UDMA_TRANSFER_MODE, g_ui8TxBuf ,
                          (void *)(SSI1_BASE),
                          sizeof(g_ui8TxBuf));

   uDMAChannelEnable(UDMA_TRANSFER_CHANNEL);
   
   printf("uDMA transfer channel enabled\n");
   //printf("--- Waiting to complete data transfer ---\n");
   //wait for DMA transfer to complete
   while(uDMAChannelIsEnabled(UDMA_TRANSFER_CHANNEL)){}
}

void Write_display(unsigned char *buff)
{

		SSIDataPut(SSI1_BASE,0x00 | 0x0);
		SSIDataPut(SSI1_BASE,0x10 | 0x0);
		SSIDataPut(SSI1_BASE,0x40 | 0x0);
		int height = 64;
		int width = 132; // same even for 128 width.
		int m_row = 0;
		int m_col = 2;
		int p = 0;
		int i, j, k = 0;
		height >>= 3;
		width >>= 3;
		//printf("Page : %i\n", i);
		for ( i = 0; i < height; i++)
		{
			// send a bunch of data in one xmission
			SSIDataPut(SSI1_BASE, 0xB0 + i + m_row);    //set page address
			SSIDataPut(SSI1_BASE, m_col & 0xf);         //set lower column address
			SSIDataPut(SSI1_BASE, 0x10 | (m_col >> 4));  //set higher column address

			DelayMs(1);

	        for( j = 0; j < 8; j++)
	        {
	        	ulDelayMs(1);
				SH1106_Disp_ACCESS();

	            for (k = 0; k < width; k++)
	            {
	            		Delay_ms(1); //1 milli Second Delay
	            		SSIDataPut(SSI1_BASE, buff[p]);
	            		//printf("value :%02x\n", buff[p]);
	            		p++;
	            }
	        }
	 	}
}

unsigned char* DMA_RX()
{
uint_fast32_t i;
unsigned char Rx[SSI_TXBUF_SIZE];

uDMAChannelAttributeDisable(UDMA_RX_CHANNEL,UDMA_ATTR_ALTSELECT |
                            UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK);

   
uDMAChannelAttributeEnable(UDMA_RX_CHANNEL, UDMA_ATTR_USEBURST);
printf("uDMA channel attributes set done\n");


uDMAChannelControlSet(UDMA_RX_CHANNEL | UDMA_PRI_SELECT,
                          SSIDATA_FRAME_SIZE | UDMA_SRC_INC_8 |
                          UDMA_DST_INC_NONE | TIMES_DMA_TRANSFER);
printf("uDMA channel control set is done\n");

   
SSIDMAEnable(SSI1_BASE, SSI_DMA_RX); // transfer the control to uDMA controller

 uDMAChannelTransferSet(UDMA_RX_CHANNEL | UDMA_PRI_SELECT,
                          UDMA_TRANSFER_MODE,(void *)(SSI1_BASE), 
						  Rx, sizeof(g_ui8TxBuf));

uDMAChannelEnable(UDMA_RX_CHANNEL);
for(i = 0; i < SSI_TXBUF_SIZE; i++)
	{
	// Wait for data to be available in the receive buffer
		while(SSIDataGetNonBlocking(SSI1_BASE, &u32Rx[i])) {}
	}
	return u32Rx;
}
int main()
{
	
    OLED_Init();
    init_uDMA();
    config_DMA_transfer();
    static unsigned char* u32Rxdata = DMA_RX();
    Write_display(u32Rxdata);
    uDMADisable();
}


void SSI_Init()
{
    unsigned int ui32SysClock;
	ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN |
                                       SYSCTL_USE_PLL | SYSCTL_CFG_VCO_240), 120000000);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

	GPIOPinConfigure(GPIO_PB4_SSI1FSS);
	GPIOPinConfigure(GPIO_PB5_SSI1CLK);
	GPIOPinConfigure(GPIO_PE4_SSI1XDAT0);
	GPIOPinConfigure(GPIO_PE5_SSI1XDAT1);

	GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_5 | GPIO_PIN_4);
	GPIOPinTypeSSI(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);

	SSIConfigSetExpClk(SSI1_BASE, ui32SysClock, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);

	SSIEnable(SSI1_BASE);
}

uDMAChannelTransferSet(UDMA_CHANNEL_SSI1RX | UDMA_PRI_SELECT,
                          UDMA_TRANSFER_MODE, (void *)(SSI1_BASE + SSI_O_DR),
                          u32Rxdata,
                          sizeof(u32Rxdata));

uDMAChannelEnable(UDMA_TRANSFER_CHANNEL | UDMA_CHANNEL_SSI1RX);