[参考译文] TM4C123GH6PM：在 Tiva-c 中获取时间的最佳方法

您好 CAN、

qiang zhang 说：

有什么更好的方法可以做到这一点吗？ 是否有更实用的方法来跟踪时间？

我建议您查看 RTC (实时计数器)计数器、其主要目的是跟踪时间。  

7.3.5 Real-Time Clock
The RTC module is designed to keep wall time. The RTC can operate in seconds counter mode. A
32.768 kHz clock source along with a 15-bit predivider reduces the clock to 1 Hz. The 1 Hz clock
is used to increment the 32-bit counter and keep track of seconds. A match register can be configured
to interrupt or wake the system from hibernate. In addition, a software trim register is implemented
to allow the user to compensate for oscillator inaccuracies using software.

7.3.5.1 RTC Counter - Seconds/Subseconds Mode
The clock signal to the RTC is provided by either of the 32.768-kHz clock sources available to the
Hibernation module. The Hibernation RTC Counter (HIBRTCC) register displays the seconds
value. The Hibernation RTC Sub Seconds register (HIBRTCSS) is provided for additional time
resolution of an application requiring less than one-second divisions.
The RTC is enabled by setting the RTCEN bit of the HIBCTL register. The RTC counter and
sub-seconds counters begin counting immediately once RTCEN is set. Both counters count up. The
RTC continues counting as long as the RTC is enabled and a valid VBAT is present, regardless of
whether VDD is present or if the device is in hibernation.
The HIBRTCC register is set by writing the Hibernation RTC Load (HIBRTCLD) register. A write
to the HIBRTCLD register clears the 15-bit sub-seconds counter field, RTCSSC, in the HIBRTCSS
register. To ensure a valid read of the RTC value, the HIBRTCC register should be read first, followed
by a read of the RTCSSC field in the HIBRTCSS register and then a re-read of the HIBRTCC register.
If the two values for the HIBRTCC are equal, the read is valid. By following this procedure, errors
in the application caused by the HIBRTCC register rolling over by a count of 1 during a read of the
RTCSSC field are prevented. The RTC can be configured to generate an alarm by setting the RTCAL0
bit in the HIBIM register. When an RTC match occurs, an interrupt is generated and displayed in
the HIBRIS register. Refer to “RTC Match - Seconds/Subseconds Mode” on page 499 for more
information.

If the RTC is enabled, only a cold POR, where both VBAT and VDD are removed, resets the RTC
registers. If any other reset occurs while the RTC is enabled, such as an external RST assertion or
BOR reset, the RTC is not reset. The RTC registers can be reset under any type of system reset
as long as the RTC and external wake pins are not enabled.

7.3.5.2 RTC Match - Seconds/Subseconds Mode
The Hibernation module includes a 32-bit match register, HIBRTCM0, which is compared to the
value of the RTC 32-bit counter, HIBRTCC. The match functionality also extends to the sub-seconds
counter. The 15-bit field (RTCSSM) in the HIBRTCSS register is compared to the value of the 15-bit
sub-seconds counter. When a match occurs, the RTCALT0 bit is set in the HIBRIS register. For
applications using Hibernate mode, the processor can be programmed to wake from Hibernate
mode by setting the RTCWEN bit in the HIBCTL register. The processor can also be programmed to
generate an interrupt to the interrupt controller by setting the RTCALT0 bit in the HIBIM register.
The match interrupt generation takes priority over an interrupt clear. Therefore, writes to the RTCALT0
bit in the Hibernation Interrupt Clear (HIBIC) register do not clear the RTCALT0 bit if the HIBRTCC
value and the HIBRTCM0 value are equal. There are several methodologies to avoid this occurrence,
such as writing a new value to the HIBRTCLD register prior to writing the HIBIC to clear the RTCALT0.
Another example, would be to disable the RTC and re-enable the RTC by clearing and setting the
RTCEN bit in the HIBCTL register.