[参考译文] TLV320AIC3106：有时、在上电配置后、差动 HPROUT 输出不工作。

您好！

首先要确保在写入这些 HPOUT 寄存器之前驱动器电源已加电且稳定。

如果电源稳定、那么我们看一下写入序列。 这些软步进寄存器是为了避免由瞬态引起的任何伪影、不应导致此处出现问题。

我建议更改以下顺序：

• 用(//**初始化输出步骤3)交换(//**初始化输出步骤2)
• 将地址14移到上面步骤2之后；在寄存器41和42之后以及寄存器37和38之前
• 配置所有其他设置后、将地址51和65移至末尾。

此致。

您好！

该寄存器42还用于控制任何喀哒声和噼啪声、因此请在您的决定中考虑这一点。

我的建议是先将寄存器51和65移至末尾、并在更改延迟之前查看这有助于控制问题。

除了耳机检测之外、寄存器14还配置输出驱动器。

此致。

我们找到了一种更快速地重现问题的方法。 我们进行了一个自动测试设置、其中编解码器被初始化、音频输出被测试、然后我们像这样连续循环、直到测试失败。 问题发生大约需要1小时。 我们能够在几个小时内测试不同的变化并获得可靠的结果。  

我在初始化函数中进行了许多更改。 我提出了您的所有建议、我还降低了 reg 42中的加电延迟、并更改了其他寄存器的顺序、我认为这些顺序可能会从中受益。

结果好、错误消失了。 该卡能够完美运行6小时的连续重新初始化。

我认为 T.I.应该为寄存器初始化序列要求编写详细的应用手册。 这显然是 IC 中的一个错误、除非我错过了应用手册。 现在可以管理错误、因为我们知道寄存器序列的秘密配方。   希望这是该器件的最后一个错误。

这是修复问题的初始化代码。

//
// ** Define a structure with CODECs configuration.
// ** Note the register must be written in the CODECs following the order of the structure (ex 0,8,9,10,98,etc.)
//
struct codec_init_table_t {
   uint8_t address, codec1_val, codec2_val, codec3_val;
} codec_init_table [] = {
/*
address ,codec1 ,codec2 ,codec3      Register Name                              Function/command configured
*/
	//GPIO, clock, misc. config
	//=========================
{0      ,0x00   ,0x00   ,0x00 }, //  Page select reg                            Always select page 0
{1      ,0x80   ,0x80   ,0x80 }, //  Software reset                             To clear potential bugs
{0      ,0x00   ,0x00   ,0x00 }, //  Page select reg                            re-select page 0
{8      ,0x20   ,0x20   ,0x20 }, //  Audio serial data I/F reg A                BCLK,WCLK=input, Dout=tri-state,Disable 3D, disable digital mic
{9      ,0x4F   ,0x4F   ,0x4F }, //  Audio serial data I/F reg B                serial data:dsp mode, 16bit timeslot, 256bit/frame,resync adc+dac, soft mute
{10     ,0x00   ,0x40   ,0x80 }, //  Audio serial data I/F reg C                Codec1:timeslot=0, Codec2:timeslot=4 (64bit offset), Codec3:timeslot=8 (128bit offset)
{11     ,0x00   ,0x00   ,0x00 }, //  Audio codec OV flag                        Flags, PLL R = dont care
{98     ,0x94   ,0x94   ,0xD4 }, //  GPIO1 Control Reg                          CODEC 1,2. GPIO 1 NOT USED, PROGRAM AS GENERAL OUTPUT = 0, CODEC 3: GPIO1 = JACK/HEADSET DETECTION INTERRUPT
{99     ,0x42   ,0x42   ,0x42 }, //  GPIO2 Control Reg                          CODEC 1,2,3. GPIO 2 future use, PROGRAM AS GENERAL OUTPUT = 0
{100    ,0x88   ,0x88   ,0x88 }, //  Additional GPIO Control reg A              SCL,SDA used as General output = 0volt
{101    ,0x01   ,0x01   ,0x01 }, //  Additional GPIO Control reg B              CODEC_CLKIN = CLKDIV_OUT, other GPIO don’t care in SPI mode
{102    ,0x00   ,0x00   ,0x00 }, //  Clock Generation Control                   CLKDIV_IN = MCLK, PLL bits = don’t care
{107    ,0x30   ,0x30   ,0x30 }, //  New Prgm ADC Digital Path and I2C Bus Cond HP filters L/R use default coef. L/R MIC are analog
{108    ,0x00   ,0x00   ,0x00 }, //  Passive Analog Signal Byp Sel in Powerdown No bypass on any analog signal during power down
{109    ,0x00   ,0x00   ,0x00 }, //  DAC Quiescent Current Adjust               default DAC reference current
{4      ,0x04   ,0x04   ,0x04 }, //  PLL prgm reg B                             PLL J= 1 dont care
{5      ,0x00   ,0x00   ,0x00 }, //  PLL prgm reg C                             PLL D (msb) = 0 dont care
{6      ,0x00   ,0x00   ,0x00 }, //  PLL prgm reg D                             PLL D (lsb) = 0 dont care
{2      ,0xAA   ,0xAA   ,0xAA }, //  Codec sample rate sel                      Codec sample rate = 8Khz = 48KHz / 6
{7      ,0x0A   ,0x0A   ,0x0A }, //  Codec datapath setup                       dual rate off, L/R ADC on L/R play
{3      ,0x10   ,0x10   ,0x10 }, //  PLL prgm reg A                             PLL disabled, Q = CLKIN / (128 x fs(ref) = 12.288M / (128 x 48000) = 2, P= dont care
{12     ,0xA0   ,0xA0   ,0xA0 }, //  Audio codec digital filter ctl             HP filter=100Hz ADC L+R, effect filter=disable, de-emphasis filter=disable
	//Inputs to ADC config
	//====================
	//**init inputs step#1
{25     ,0x00   ,0x00   ,0x80 }, //  MICBIAS ctl                                codec1-2:MICBIAS=disabled, codec3:MINBIAS=2.5V
	//**init inputs step#2
{17     ,0xFF   ,0xFF   ,0x0F }, //  MIC3L/R to left ADC                        codec1-2:micL/R not connected  to left ADC. codec3 micL connected 0dB to left ADC
{18     ,0xFF   ,0xFF   ,0xFF }, //  MIC3L/R to right ADC                       codec:micL/R not connected  to right ADC.
{19     ,0x00   ,0x80   ,0x78 }, //  LINE1L to L ADC ctl                        Line1L to L ADC= codec1: 0dB, codec2: 0dB, codec3: n.c. Line1L: codec1=SE, codec2=FD, codec3=SE,!! KEEP LEFT ADC POWER DOWN !!
{20     ,0x78   ,0x78   ,0x78 }, //  LINE2L to L ADC ctl                        Line2L to L ADC= codec1-2-3: n.c. Disable weakly biased on input L ADC
{21     ,0x78   ,0xF8   ,0xF8 }, //  LINE1R to L ADC ctl                        Line1R to L ADC= codec1-2-3: n.c. Line1R: codec1=SE, codec2=FD, codec3=FD
{22     ,0x00   ,0x80   ,0x80 }, //  LINE1R to R ADC ctl                        Line1R to R ADC= codec1: 0dB, codec2: 0dB, codec3: 0dB. Enable R ADC. Line1R: codec1=SE, codec2=FD, codec3=FD, !! KEEP LEFT ADC POWER DOWN !!
{23     ,0x78   ,0x78   ,0x78 }, //  LINE2R to R ADC ctl                        Line2R to R ADC= codec1-2-3: n.c. Disable weakly biased on input R ADC
{24     ,0x78   ,0xF8   ,0x78 }, //  LINE1L to R ADC ctl                        Line1L to R ADC= codec1-2-3: n.c. Line1L: codec1=SE, codec2=FD, codec3=SE
	//**init inputs step#3
{15     ,0x15   ,0x10   ,0x3C }, //  Left ADC PGA gain ctl                      Left ADC not muted, PGA Gain: codec1 HDT mouth1= 10.5dB, codec2 Radio in= 8dB, codec3 micro= 30dB
{16     ,0x15   ,0x10   ,0x00 }, //  Right ADC PGA gain ctl                     Right ADC not muted, PGA Gain: codec1 HDT mouth1= 10.5dB, codec2 Radio in= 8dB, codec3 n.c.= 0dB
	
	//**init inputs step#5
{19     ,0x04   ,0x84   ,0x7C }, //  LINE1L to L ADC ctl                        Line1L to L ADC= codec1: 0dB, codec2: 0dB, codec3: n.c. Line1L: codec1=SE, codec2=FD, codec3=SE !! LEFT ADC POWER ON !!
{22     ,0x04   ,0x84   ,0x84 }, //  LINE1R to R ADC ctl                        Line1R to R ADC= codec1: 0dB, codec2: 0dB, codec3: 0dB. Enable R ADC. Line1R: codec1=SE, codec2=FD, codec3=FD !! RIGHT ADC POWER ON !!

	//DAC to outputs config
	//=====================
	//**init outputs step #1
{43     ,0x01   ,0x01   ,0x01 }, //  L DAC digital volume ctl                   L DAC is not Muted, L DAC volume = -0.5dB to compensate Oct 28,2019 new output audio path configuration (DAC_L1 instead of DAC_L2)
{44     ,0x01   ,0x01   ,0x01 }, //  R DAC digital volume ctl                   R DAC is not Muted, R DAC volume = -0.5dB to compensate Oct 28,2019 new output audio path configuration (DAC_R1 instead of DAC_R2)
	//**init outputs step #new 2 (old 3)
{41     ,0x00   ,0x00   ,0x00 }, //  DAC out switching ctl                      L DAC uses DAC_L1 path (less noise), R DAC use DAC_R1 path (less noise), L & R DAC volume have independent ctl
{42     ,0x16   ,0x16   ,0x16 }, //  Output driver pop reduction                drv power on time=10us, ramp-up step=1ms, weakly CM from bandgap ref
	//**init outputs step #3-a  (old2)
{37     ,0xC0   ,0xC0   ,0xD0 }, //  AC pwr and output driver                   L/R ADC power up, codec1-2:HPLCOM=diff, codec3:HPLCOM=VCM
{38     ,0x04   ,0x04   ,0x0C }, //  high power output driver ctl               codec1-2:HPRCOM=diff, codec3:HPRCOM=VCM. Short circuit protection enabled
{40     ,0x40   ,0x40   ,0x40 }, //  high power output stage ctl                VCM = 1.5v, disable:LINE2L, LINE2R, soft stepping 1 per fs
	//**init outputs step #3-b
{13     ,0x16   ,0x16   ,0x96 }, //  headset/button detect reg A                Codec1-2: disable headset detection. Codec3: enable headset detection, jack det=512ms, button=16ms
{14     ,0xC0   ,0xC0   ,0x80 }, //  headset/button detect reg B                Codec1-2:ac coupled, Diff out, Codec3 ac coupled, single ended out.

	//**init outputs step #4 (HPLOUT)
{47     ,0x80   ,0x80   ,0x80 }, //  DAC_L1 to HPLOUT volume                    DAC_L1 goes to HPLOUT with 0dB attenuation on codecs 1,2,3

	//**init outputs step #5 (HPROUT)
{64     ,0x80   ,0x80   ,0x80 }, //  DAC_R1 to HPROUT volume                    DAC_R1 goes to HPROUT with 0dB attenuation on codecs 1,2,3

	//** outputs FINAL step: Texas Inst. says that reg 58, 72, 51 then 65 should be written at the end
{58     ,0x00   ,0x00   ,0x00 }, //  HPLCOM output level ctl                    HPLCOM disable. Overriden by register 37 bit5,4 in differential mode
{72     ,0x00   ,0x00   ,0x00 }, //  HPRCOM output level ctl                    HPRCOM disable. Overriden by register 38 bit5,4,3 in differential mode
{51     ,0x11   ,0x31   ,0x71 }, //  HPLOUT output level ctl                    HPLOUT 0dB level, Muted!!, weak driver when disable, Full power-up. GAIN: codec1=1dB, codec2=3dB, codec3=7dB
{51     ,0x19   ,0x39   ,0x79 }, //  HPLOUT output level ctl                    HPLOUT 0dB level, not Muted, weak driver when disable, Full power-up. GAIN: codec1=1dB, codec2=3dB, codec3=7dB
{65     ,0x11   ,0x31   ,0x71 }, //  HPROUT output level ctl                    HPROUT 0dB level, Muted!!, weak driver when disable, Full power-up. GAIN: codec1=1dB, codec2=3dB, codec3=7dB
{65     ,0x19   ,0x39   ,0x79 }  //  HPROUT output level ctl                    HPROUT 0dB level, not Muted, weak driver when disable, Full power-up. GAIN: codec1=1dB, codec2=3dB, codec3=7dB

};