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[参考译文] Linux/TLV320AIC3100:TLV320AIC3100 BCLK 无输出

Guru**** 2478765 points
Other Parts Discussed in Thread: TLV320AIC3100

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https://e2e.ti.com/support/audio-group/audio/f/audio-forum/816838/linux-tlv320aic3100-tlv320aic3100-bclk-no-output

器件型号:TLV320AIC3100

工具/软件:Linux

硬件:imx6q AUD3端口与 TLV320AIC3100连接

软件 Linux:3.14.28

我想将 TLV320AIC3100配置 为 I2S 主器件。

我的编解码器源代码来自 Linux 内核。

现在 、MCLK 上的24MHz 时钟正常。

我的寄存器映射如下所示:

---------- [组= 0]-----
    00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
----------------------------------
00 | 00 01 66 03 A1 07 14 90 00 88 82 00 80
10 | 08 00 88 82 80 04 00 00 01 0c 00 88 00
20 | 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30 | 00 00 02 32 12 03 02 02 11 10 00 01 04 00 14
40 | 00 D8 00 6F 38 00 00 00 00 00 00 ee 10 D8 7e E3
50 | 00 00 80 00 00 00 00 00 7f 00 00 00 00 00 00 00 00 00 00 00 00
60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 74 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
A0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
B0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
C0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
D0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
E0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

内核日志:

[2.235413]  ASOC:注册编解码器'tlv320aic31xx-codec.2-0018'

[2.372431]##aic31xx_SET_DAI_SYSCLK:CLK_id = 0、freq = 24000000、dir = 0
[2.385707]## aic31xx_set_Dai_SYSCLK:P_div = 2、I=0
[2.393066] tlv320aic31xx sound-tlv32.23:tlv320aic31xx-hifi <->202c000.SSI 映射正常

root@imx6qsabersd:~# aplay temp.wav

## aic31xx_hw_params:宽度16速率44100

[30.128044]  PLL 7.5264/2 dosr 128 n 8 m 2 aosr 128 n 8 m 2 BCLK_n 8

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    Ya LIN、  

    您共享的寄存器配置显示了在24MHz 时钟下主控模式的正确配置。  BLCK 设置为输出、BCLK 分频器加电并设置为正确的值、它从 DAC_CLK 获取 BCLK。  N 和 M 分频器也已加电、 因此我看不到您没有看到 BCLK 的明显原因。  是否有可能将 BCLK 线路端接至一个低阻抗负载?

    此致、

    -Steve Wilson  

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    Ya LIN、  

    我没有听到您的反馈。  如果您仍需要有关此方面的帮助、请告诉我。

    此致、

    -Steve Wilson

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好 Steve Wilson

    现在,在 将 reg 0x3f 设置为 d6后,BCLK 输出正常。