[参考译文] TMS320F280041：低功耗模式：停止未实现最低功耗

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1116233/tms320f280041-low-power-mode-halt-not-achieving-lowest-power

您好！

我正在编写一个需要低功耗模式的应用。 在 TMS320F28004x 数据表的下图中、通告在 HALT 模式中使用 DC-DC 时、我"通常"应该在馈送 Vdio 和 VDDA 的3V3线路上看到1.7 + 0.2 ~ 1.9mA。 不过、我看到的更像是14mA。 我正在禁用闪存和 PLL、但我仍然看到这些结果。 请给出建议。

下面列出了我从 RAM 运行的低功耗模式功能。

#pragma CODE_SECTION(lpm_enterLowPowerMode, "ramfuncs");
void lpm_enterLowPowerMode(void)
{
    /*      Unlock locked registers     */
    EALLOW;

    /*      Check the arguments.        */
    ASSERT(Flash_isCtrlBaseValid(FLASH0CTRL_BASE));

    /*       Write the power mode to the appropriate register.      */
    HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) = (HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) & ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t) FLASH_BANK0 * 2U))) | ((uint32_t) FLASH_BANK_PWR_SLEEP << ((uint32_t) FLASH_BANK0 * 2U));

    /*      Write the power mode to the appropriate register.       */
    HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) = (HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) & ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t) FLASH_BANK1 * 2U))) | ((uint32_t) FLASH_BANK_PWR_SLEEP << ((uint32_t) FLASH_BANK1 * 2U));

    /*      Write the power mode to the appropriate register.       */
    HWREG(FLASH0CTRL_BASE + FLASH_O_FPAC1) = (HWREG(FLASH0CTRL_BASE + FLASH_O_FPAC1) & ~(uint32_t) FLASH_FPAC1_PMPPWR) | (uint32_t) FLASH_PUMP_PWR_SLEEP;

    /*      Set Idle to Halt        */
    HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & ~(uint32_t) SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HALT;


    /*      Disable PLL     */
    HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN);

    /*      Enter Halt Mode     */
    IDLE;

    /*      Power Up Flash         */
    /*       Write the power mode to the appropriate register.      */
    HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) = (HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) & ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t) FLASH_BANK0 * 2U))) | ((uint32_t) FLASH_BANK_PWR_ACTIVE << ((uint32_t) FLASH_BANK0 * 2U));

    /*      Write the power mode to the appropriate register.       */
    HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) = (HWREG(FLASH0CTRL_BASE + FLASH_O_FBFALLBACK) & ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t) FLASH_BANK1 * 2U))) | ((uint32_t) FLASH_BANK_PWR_ACTIVE << ((uint32_t) FLASH_BANK1 * 2U));

    /*      Write the power mode to the appropriate register.       */
    HWREG(FLASH0CTRL_BASE + FLASH_O_FPAC1) = (HWREG(FLASH0CTRL_BASE + FLASH_O_FPAC1) & ~(uint32_t) FLASH_FPAC1_PMPPWR) | (uint32_t) FLASH_PUMP_PWR_ACTIVE;

    EDIS;
}