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void InitMcbspb(void)
{
// McBSP-B register settings
McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
//Loopback mode does not apply here
//McbspbRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
McbspbRegs.MFFINT.all=0x0; // Disable all interrupts
McbspbRegs.RCR1.all=0x0;
McbspbRegs.RCR2.all=0x0; // Single-phase frame, No companding (Receive)
McbspbRegs.RCR1.bit.RFRLEN1 = MCBSP_RECEIVE_FRAME_LENGTH(McBSPNumRxWords);
McbspbRegs.RCR2.bit.RDATDLY = MCBSP_0_BIT_DELAY;
//McbspbRegs.RCR2.bit.RFIG = 1; //Ignore incoming frame-sync pulses (the FPGA only sends one for the whole packet)
McbspbRegs.XCR1.all=0x0;
McbspbRegs.XCR2.all=0x0; // Single-phase frame, No companding (Transmit)
McbspbRegs.XCR1.bit.XFRLEN1 = MCBSP_TRANSMIT_FRAME_LENGTH(McBSPNumTxWords);
McbspbRegs.XCR2.bit.XDATDLY = MCBSP_0_BIT_DELAY;
InitMcbspb16bit(); //Sets RCR1.bit.RWDLEN1 and XCR1.bit.XWDLEN1
McbspbRegs.PCR.bit.FSXM = MCBSP_INTERNAL_TX_FRAME_SYNC; // FSX generated internally, FSR derived from an external source
McbspbRegs.PCR.bit.CLKXM = MCBSP_INTERNAL_TX_CLK; // CLK-TX is driven by the sample rate generator clock
McbspbRegs.PCR.bit.CLKRM = MCBSP_INTERNAL_RX_CLK; // CLK-RX is driven by the sample rate generator clock
McbspbRegs.PCR.bit.CLKXP = MCBSP_TX_DATA_UPDATE_ON_FALLING; // TX data clocked on falling edges (should be sampled on rising)
McbspbRegs.PCR.bit.CLKRP = MCBSP_RX_SAMPLED_ON_FALLING; // RX data sampled on falling edges
//CLKSM=1 and SCLKME=0 defines the sample-rate-generator based on the internal sample rate generator
McbspbRegs.PCR.bit.SCLKME = 0;
McbspbRegs.SRGR2.bit.CLKSM = MCBSP_SAMPLE_RATE_GENERATOR_LSPCLK;
McbspbRegs.SRGR2.bit.FPER = MCBSP_FRAME_SYNC_PERIOD(16); // FPER = 16 bits plus 1 FS bit
McbspbRegs.SRGR1.bit.FWID = MCBSP_FRAME_SYNC_PULSE_WIDTH(1); // Frame Width = 1 CLKG period
McbspbRegs.SRGR1.bit.CLKGDV = MCBSP_CLOCK_DIVIDE(McBSPClockDivider);// CLKG frequency = LSPCLK/(x) (or SYSCLKOUT/{x*4})
//For debug: stop the McBSP clock on emulator halt:
McbspbRegs.SPCR2.bit.FREE = 0; //Stop the clock on breakpoint halt
McbspbRegs.SPCR2.bit.SOFT = 0; //And don't finish the word
delay_loop(); // Wait at least 2 SRG clock cycles
McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
clkg_delay_loop(); // Wait at least 2 CLKG cycles
McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
//Connect DMA channel 5 to McBSPA receive:
DMACH5AddrConfig((U16 *)&McBSPRxDataUInt[0], (U16*)&McbspbRegs.DRR1.all);
EALLOW;
//The inner-loop is the burst per trigger:
DMA5_WRITE_BURST_SIZE(1); //One "DATASIZE" value at a time
DMA5_WRITE_SRC_BURST_STEP(0); //The transfer-loop will increment
DMA5_WRITE_DST_BURST_STEP(0); //All transmissions written to a single address (no increment)
//The outer-loop transfers a total of BURST_SIZE * TRANSFER_SIZE words.
DMA5_WRITE_TRANSFER_SIZE(McBSPNumRxWords); //Number of transfers of 1 word(burst) at a time
DMA5_WRITE_SRC_TRANSFER_STEP(0); //Source address does not change
DMA5_WRITE_DST_TRANSFER_STEP(1); //1 word increment after each 1-word received
DMA5_WRITE_SOURCE_WRAP_SIZE(0xFFFF); // Wrap disabled
DMA5_WRITE_SOURCE_WRAP_STEP(0xFFFF); // Wrap disabled
DMA5_WRITE_DST_WRAP_SIZE(0xFFFF); // Wrap disabled
DMA5_WRITE_DST_WRAP_STEP(0xFFFF); // Wrap disabled
// Set up MODE Register:
DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = DMA_MREVTB; // Triggered by DMA_MREVTB
DmaRegs.CH5.MODE.bit.PERINTSEL = 5; // DMA channel 5
DmaRegs.CH5.MODE.bit.CHINTE = CHINT_DISABLE; // No Transfer-complete interrupt
DmaRegs.CH5.MODE.bit.DATASIZE = SIXTEEN_BIT; // 16-bit data size transfers
DmaRegs.CH5.MODE.bit.CONTINUOUS = CONT_DISABLE; // Channel is disabled after transfer is complete
DmaRegs.CH5.MODE.bit.ONESHOT = ONESHOT_DISABLE; // Oneshot disabled (One burst per event)
DmaRegs.CH5.MODE.bit.CHINTMODE = CHINT_END; // Generate interrupt to CPU at end of transfer
DmaRegs.CH5.MODE.bit.PERINTE = PERINT_ENABLE; // Peripheral interrupt enable
DmaRegs.CH5.MODE.bit.OVRINTE = OVERFLOW_DISABLE; // Disable the overflow interrupt
// Clear any spurious flags:
DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
EDIS;
StartDMACH5(); //The transfer starts when the event/interrupt occurs:
//When the McBSP receives a word, it generates the REVT events to the DMA-engine, which reads the word.
//It is assumed the transfer is complete by the end of the HSL.
//Connect DMA channel 6 to McBSPB transmit:
DMACH6AddrConfig((U16*)&McbspbRegs.DXR1.all, (U16 *)&McBSPTxDataUInt[0]);
EALLOW;
//The inner-loop is the burst per trigger:
DMA6_WRITE_BURST_SIZE(1); //One "DATASIZE" value at a time
DMA6_WRITE_SRC_BURST_STEP(0); //The transfer-loop will increment
DMA6_WRITE_DST_BURST_STEP(0); //All transmissions written to a single address (no increment)
//The outer-loop transfers a total of BURST_SIZE * TRANSFER_SIZE words.
DMA6_WRITE_TRANSFER_SIZE(McBSPNumTxWords); //Number of transfers of 1 word(burst) at a time
DMA6_WRITE_SRC_TRANSFER_STEP(1); //1 word increment after each 1-word transmitted
DMA6_WRITE_DST_TRANSFER_STEP(0); //Destination address does not change
DMA6_WRITE_SOURCE_WRAP_SIZE(0xFFFF); // Wrap disabled
DMA6_WRITE_SOURCE_WRAP_STEP(0xFFFF); // Wrap disabled
DMA6_WRITE_DST_WRAP_SIZE(0xFFFF); // Wrap disabled
DMA6_WRITE_DST_WRAP_STEP(0xFFFF); // Wrap disabled
// Set up MODE Register:
DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = DMA_MXEVTB; // Triggered by DMA_MXEVTB
DmaRegs.CH6.MODE.bit.PERINTSEL = 6; // DMA channel 6
DmaRegs.CH6.MODE.bit.CHINTE = CHINT_DISABLE; // No Transfer-complete interrupt
DmaRegs.CH6.MODE.bit.DATASIZE = SIXTEEN_BIT; // 16-bit data size transfers
DmaRegs.CH6.MODE.bit.CONTINUOUS = CONT_DISABLE; // Channel is disabled after transfer is complete
DmaRegs.CH6.MODE.bit.ONESHOT = ONESHOT_DISABLE; // Oneshot disabled (One burst per event)
DmaRegs.CH6.MODE.bit.CHINTMODE = CHINT_END; // Generate interrupt to CPU at end of transfer
DmaRegs.CH6.MODE.bit.PERINTE = PERINT_ENABLE; // Peripheral interrupt enable
DmaRegs.CH6.MODE.bit.OVRINTE = OVERFLOW_DISABLE; // Disable the overflow interrupt
// Clear any spurious flags:
DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
EDIS;
StartDMACH6(); //The transfer starts when the event/interrupt occurs:
//Force an event (trigger) onto the DMA engine by calling DMA6_FORCE_TRIGGER(), which inserts an event into DMA6. Then
//the McBSP transmit-register is written with the first array element. The McBSP produces an XEVT when XRDY is true,
//which kicks off the next word-write. It is assumed the transfer is complete by the end of the HSL.
}
