Other Parts Discussed in Thread: TMS320F28075
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器件型号：TMS320F28075 大家好、
我正在使用 TMS320F28075控制器并尝试通过 SPI 与外部闪存器件通信。 在 我启用一个20kHz 中断"appTask"前、一切都正常、代码如下。 这个中断内的代码是关键的、所以我不能将其禁用或缩小。
启用此20kHz 中断后、并非所有数据都能正确写入外部闪存或从外部闪存中正确读取。 只有小块数据被成功写入/读取、且数量是随机的。
看起来中断会干扰 SPI 通信。 我本来以为 SPI 的外设是外部的、并且可以独立于主线程或中断工作。
是否可以启用以下中断并 使 SPI 通信正常工作？ 或者我是否做了一些错误的事情？
如果有任何帮助，将不胜感激。
// -------------------------- interrupt code --------------------------------------------------
/* Set the interrupt vector */
EALLOW;
{
PieVectTable.TIMER0_INT = &appTask;
}
EDIS;
/* Configure CPU-Timer 0: */
ConfigCpuTimer( &CpuTimer0,
( SYSCLK / 1000000 ),
MAINTENANCE_PERIOD_uS );
CpuTimer0Regs.TCR.all = 0x4000; // Use write-only instruction to set TSS bit = 0
/* Enable CPU int1 which is connected to CPU-Timer 0 */
IER |= M_INT1;
/* Enable TINT0 in the PIE: Group 1 interrupt 7 */
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
/* Enable global Interrupts and higher priority real-time debug events: */
EINT;
ERTM;
// -------------------------- interrupt code --------------------------------------------------
// ------------------------- SPI port init -----------------------------------------------------
/* Control Register (SPICCR).... 'normal' values
* Clock polarity normal
* Loopback off
* SPI Character length (see SPRUHM9B Table 17-9) 0xF => 16-bits
* SPI High Speed mode disabled (not allowed with selected GPIO - see SPRUHM9B section 17.2.2)
*/
SPI_PORT.SPICCR.bit.CLKPOLARITY = 1;
SPI_PORT.SPICCR.bit.SPILBK = 0;
SPI_PORT.SPICCR.bit.SPICHAR = 0x0F;
SPI_PORT.SPICCR.bit.HS_MODE = 0; //sww12jan16
/* SPI Operation Control Register (SPICTL)....
* Disable rx overrun interrupt
* Clock phase normal
* Master mode
* Transmit enabled
* Enable SPI interrupt
*/
SPI_PORT.SPICTL.bit.OVERRUNINTENA = 0;
SPI_PORT.SPICTL.bit.CLK_PHASE = 1;
SPI_PORT.SPICTL.bit.MASTER_SLAVE = 1;
SPI_PORT.SPICTL.bit.TALK = 1;
SPI_PORT.SPICTL.bit.SPIINTENA = 1;
/* SPI Status Register (SPISTS).... 'normal' values
* Clear any outstanding flags
*/
SPI_PORT.SPISTS.all = 0;
/* SPI Baud Rate Register (SPIBRR)
* max baud rate must be less than the max gpio toggle frequency = 25MHz (See SPRUHM9B section 17.3.5 and SPRS902B section 5.7.6.1)
* and less than the slowest device - TC77 max frequency = 7MHz (could select different rates for different devices)
* For SPIBRR > 2, SPI Baud Rate LSPCLK/(SPIBRR+1), where LSPCLK = SYSCLK/4 = 30Mhz
* For SPIBRR = 0, 1, or 2, baud = LSPCLK/4 = 7.5MHz
*/
SPI_PORT.SPIBRR.bit.SPI_BIT_RATE = 4; /* 30/(4+1) = 6MHz jan16 */
/* SPI FIFO Transmit Register (SPIFFTX)
* 0xE0 => fifo enable; enhancements enable; tx enable
* 0x63 => clear outstanding INT; interrupt on FiFo <=3
* !!DAVEC!! set FiFo for best latency at 5MHz
*/
/* Reset all to default */
SPI_PORT.SPIFFTX.all = 0;
SPI_PORT.SPIFFTX.all = 0xE063;
/* SPI FIFO Receive Register (SPIFFRX)
* 0x60 => clear overflow; rx enable;
* 0x61 => clear outstanding INT; interrupt on FiFo >= 1
*/
/* Reset all to default */
SPI_PORT.SPIFFRX.all = 0;
SPI_PORT.SPIFFRX.all = 0x6061;
SPI_PORT.SPICCR.bit.SPILBK = 0;
/* SPI FIFO Control Register (SPIFFCT)
* Delay between FiFo and transmit Shift Reg.
*/
SPI_PORT.SPIFFCT.bit.TXDLY = 0x00;
/* SPI Priority Control Register (SPIPRI)
* Free-run on emulation suspend
* SPISTE non-inverted (not used here anyway)
* Normal 4-wire SPI mode
*/
SPI_PORT.SPIPRI.bit.FREE = 1;
SPI_PORT.SPIPRI.bit.STEINV = 0;
SPI_PORT.SPIPRI.bit.TRIWIRE = 0;
// --------------------------------------------------------------感谢你能抽出时间。 