请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。
器件型号：TMS320F280025C-Q1 您好、支持团队、
我可以使用 DMA 读取 ADC 结果、然后我想读取 GPIO 引脚的状态。
但是、当我在下面的代码中将 DMA 源"&AdcaResultRegs.ADCRESULT0"替换为"&GpioDataReadRegs.GPADAT_R"或"&GpioDataRegs.GPADAT.All"时、我无法获得正确的引脚状态。
虽然有高引脚和低引脚、整个寄存器被读取为0。
在使用 DMA 读取 GPIO 引脚状态时、我是否应该考虑任何因素？
读取 ADC 结果代码=>正常工作
EALLOW;
// DMA_configAddresses DMA channel 1 set up for ADCA
/* Set up SOURCE address. */
DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (u32)&AdcaResultRegs.ADCRESULT0;
/* Point to beginning of source buffer */
DmaRegs.CH2.SRC_ADDR_SHADOW = (u32)&AdcaResultRegs.ADCRESULT0;
/* Set up DESTINATION address. */
DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (u32)u16AdcByDma;
/* Point to beginning of destination buffer */
DmaRegs.CH2.DST_ADDR_SHADOW = (u32)u16AdcByDma;
// Set up BURST registers.
DmaRegs.CH2.BURST_SIZE.bit.BURSTSIZE = 0u; // Number of words(X-1) x-ferred in a burst.
DmaRegs.CH2.SRC_BURST_STEP = 0u;// Increment source addr between each word x-ferred.
DmaRegs.CH2.DST_BURST_STEP = 0u;// Increment dest addr between each word x-ferred.
// Set up TRANSFER registers.
DmaRegs.CH2.TRANSFER_SIZE = 99u; // Number of bursts per transfer, DMA interrupt will occur after completed transfer.
DmaRegs.CH2.SRC_TRANSFER_STEP = 0u;// TRANSFER_STEP is ignored when WRAP occurs.
DmaRegs.CH2.DST_TRANSFER_STEP = 1;// TRANSFER_STEP is ignored when WRAP occurs.
/* disable wrapping */
DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFFu;
DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFFu;
// Set up trigger selection in the CMA/CLA trigger source selection registers. These are considered part of system control.
DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = DMA_TRIGGER_ADCA1;
// Set peripheral interrupt select bits to the channel number (legacy bits - hard coded to channel)
DmaRegs.CH2.MODE.bit.PERINTSEL = 2u;
// Write the configuration to the mode register.
DmaRegs.CH2.MODE.bit.DATASIZE = 0u; /* DMA transfers 16 bits at a time. */
DmaRegs.CH2.MODE.bit.CONTINUOUS = 1u;
DmaRegs.CH2.MODE.bit.ONESHOT = 0u;
// Set the peripheral interrupt trigger enable bit.
DmaRegs.CH2.MODE.bit.PERINTE = 1u;
DmaRegs.CH2.MODE.bit.OVRINTE = 0u;
/* the DMA channel interrupt will be generated at the end of the transfer */
DmaRegs.CH2.MODE.bit.CHINTMODE = 1u;
PieVectTable.DMA_CH2_INT = &dmach2ISR; /* Map ISR functions */
DmaRegs.CH2.MODE.bit.CHINTE = 1u; /* enableInterrupt */
/* Write a one to the clear bit to clear the peripheral trigger flag. */
// Clear any spurious flags: Interrupt flags and sync error flags
DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1u;
DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;
CPU_EnableIRQ(INT_DMA_CH2); /* Enable DMA 1 Interrupt */
DmaRegs.CH2.CONTROL.bit.RUN = 1u;
EDIS;
读取引脚状态代码=>读取全部0
/* Set up SOURCE address. */ DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (u32)&GpioDataReadRegs.GPADAT_R; /* Point to beginning of source buffer */ DmaRegs.CH2.SRC_ADDR_SHADOW = (u32)&GpioDataReadRegs.GPADAT_R;
/* Set up SOURCE address. */ DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (u32)&GpioDataRegs.GPADAT.all; /* Point to beginning of source buffer */ DmaRegs.CH2.SRC_ADDR_SHADOW = (u32)&GpioDataRegs.GPADAT.all;
此致、
问题
