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器件型号：TMS320F28069 我的主循环变量('tick counter')卡在固定数字上的情况非常奇怪。 当我添加全局空虚拟变量(声明和定义但未使用)时、此行为消失。 这指向了我认为存在的内存错误、但无论我如何处理链接器文件、行为都不会消失。 此外、我通过向堆栈填充固定值来检查堆栈溢出、并且它保持在其界限内。 这是我的链接器文件：
/* // TI File $Revision: /main/3 $ // Checkin $Date: March 3, 2011 13:45:53 $ //########################################################################### // // FILE: F28069.cmd // // TITLE: Linker Command File For F28069 Device // //########################################################################### // $TI Release: F2806x Support Library v2.06.00.00 $ // $Release Date: Fri Feb 12 19:15:11 IST 2021 $ // $Copyright: // Copyright (C) 2009-2021 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in <base>\headers\cmd // // For BIOS applications add: F2806x_Headers_BIOS.cmd // For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd ========================================================= */ /* ====================================================== // For Code Composer Studio prior to V2.2 // -------------------------------------- // 1) Use one of the following -l statements to include the // header linker command file in the project. The header linker // file is required to link the peripheral structures to the proper // locations within the memory map */ /* Uncomment this line to include file only for non-BIOS applications */ /* -l F2806x_Headers_nonBIOS.cmd */ /* Uncomment this line to include file only for BIOS applications */ /* -l F2806x_Headers_BIOS.cmd */ /* 2) In your project add the path to <base>\headers\cmd to the library search path under project->build options, linker tab, library search path (-i). /*========================================================= */ /* Define the memory block start/length for the F2806x PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F28069 are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. Contiguous SARAM memory blocks can be combined if required to create a larger memory block. */ MEMORY { PAGE 0 : /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */ CLAPROG : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */ OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */ FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */ FLASHF : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */ FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */ FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */ FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */ FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */ CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ FPUTABLES : origin = 0x3FD590, length = 0x0006A0 /* FPU Tables in Boot ROM */ IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */ IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */ ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM01 : origin = 0x000050, length = 0x0007B0 /* on-chip RAM block M0 */ //RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ CLARAM0 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */ CLARAM1 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */ RAML4L5 : origin = 0x00A000, length = 0x004000 /* on-chip RAM block L4 */ // RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */ RAML6 : origin = 0x00E000, length = 0x002000 /* on-chip RAM block L6 */ RAML7 : origin = 0x010000, length = 0x002000 /* on-chip RAM block L7 */ RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */ FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */ CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 } /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ .cinit : > FLASHE, PAGE = 0 .pinit : > FLASHA, PAGE = 0 .text : > FLASHA, PAGE = 0 codestart : > BEGIN, PAGE = 0 ramfuncs : LOAD = FLASHD, RUN = RAML0, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), LOAD_SIZE(_RamfuncsLoadSize), PAGE = 0 Cla1Prog : LOAD = FLASHC, RUN = CLAPROG, LOAD_START(_Cla1funcsLoadStart), LOAD_END(_Cla1funcsLoadEnd), RUN_START(_Cla1funcsRunStart), LOAD_SIZE(_Cla1funcsLoadSize), PAGE = 0 Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 csmpasswds : > CSM_PWL_P0, PAGE = 0 csm_rsvd : > CSM_RSVD, PAGE = 0 /* Allocate uninitialized data sections: */ .stack : > RAMM01, PAGE = 1 .ebss : > RAML4L5, PAGE = 1 .esysmem : > RAML6, PAGE = 1 .cio : > RAML6, PAGE = 1 .scratchpad : > CLARAM0, PAGE = 1 .bss_cla : > CLARAM1, PAGE = 1 .const_cla : > CLARAM1, PAGE = 1 /* Initialized sections to go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > FLASHE, PAGE = 0 .switch : > FLASHE, PAGE = 0 /* Allocate IQ math areas: */ // IQmath : > FLASHA, PAGE = 0 /* Math Code */ // IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD /* Allocate FPU math areas: */ FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD /* DMARAML5 : > RAML5, PAGE = 1 DMARAML6 : > RAML6, PAGE = 1 DMARAML7 : > RAML7, PAGE = 1 DMARAML8 : > RAML8, PAGE = 1 */ /* Uncomment the section below if calling the IQNexp() or IQexp() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD { IQmath.lib<IQNexpTable.obj> (IQmathTablesRam) } */ /* Uncomment the section below if calling the IQNasin() or IQasin() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD { IQmath.lib<IQNasinTable.obj> (IQmathTablesRam) } */ /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS, PAGE = 0, TYPE = DSECT } /* //=========================================================================== // End of file. //=========================================================================== */
我真的不知道在哪里可以寻找问题、有人会提出建议？
