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[参考译文] TMS320F28069M:将 INSTASPIN 程序加载到闪存中

Guru**** 2516370 points
Other Parts Discussed in Thread: LAUNCHXL-F28069M

请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1169668/tms320f28069m-loading-instaspin-program-to-flash

器件型号:TMS320F28069M
主题中讨论的其他器件:LAUNCHXL-F28069M

您好! 我的项目基于 INSTASPIN 实验室。 我采用了 lab1b 并添加了我的代码。 现在、我要将该程序加载到控制器的闪存中。 我的板基于  LAUNCHXL-F28069M。 因此、TRST、TDO 和 GPIO34上具有2.2k Ω 的下拉电阻。 在 TDO 和 GPIO34上的带子之后有910ohm 上拉电阻。 我的 GPIO34引脚配置为通用输入。 我认为我的项目中有必要的代码:

extern uint16_t *RamfuncsLoadStart, *RamfuncsLoadEnd, *RamfuncsRunStart;

#ifdef CSM_ENABLE
extern uint16_t *econst_start, *econst_end, *econst_ram_load;
extern uint16_t *switch_start, *switch_end, *switch_ram_load;
#endif
#endif

void System_Init()
{
    #ifdef FAST_ROM_V1p6
      uint_least8_t ctrlNumber = 1;
    #endif

      // Only used if running from FLASH
      // Note that the variable FLASH is defined by the project
      #ifdef FLASH
      // Copy time critical code and Flash setup code to RAM
      // The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
      // symbols are created by the linker. Refer to the linker files.
      memCopy((uint16_t *)&RamfuncsLoadStart,(uint16_t *)&RamfuncsLoadEnd,(uint16_t *)&RamfuncsRunStart);

      #ifdef CSM_ENABLE
        //copy .econst to unsecure RAM
        if(*econst_end - *econst_start)
          {
            memCopy((uint16_t *)&econst_start,(uint16_t *)&econst_end,(uint16_t *)&econst_ram_load);
          }

        //copy .switch ot unsecure RAM
        if(*switch_end - *switch_start)
          {
            memCopy((uint16_t *)&switch_start,(uint16_t *)&switch_end,(uint16_t *)&switch_ram_load);
          }
      #endif
      #endif
}

我调用的第一个函数是这个 System_init()。 我n`t 闪存定义。我不使用 CSM。 我将使用 F28069M.cmd 编译程序、作为链接器文件。 我测试了开关的几个组合- TRST 连接到编程器、而不是 GPIO34高电平和低电平。 没有影响。 微控制器上没有任何东西。 我出了什么问题? GPIO34上的偏离器是否有可能阻止在它上注册逻辑"1"? 电压低于3V (我认为是2.5V)? 我是否必须将 hal.c 中的 GPIO34配置为保留函数?   

以下是我的整个代码:

e2e.ti.com/.../CNCRouter-simple-program-v08-11-2022.rar

有什么建议吗?

谢谢!

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、我们的链接器文件专家 Pavlin 将很快回答您的问题、感谢您的耐心等待。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    谢谢! 我找到了这个主题: 单击

    我想我已经做了所有在那里被批评的事情,但这些仍然没有 proges。 我在预分段中定义了闪存。 我有 memcopy.c、codestartbranch.asm、RAM_LINK 被从编译中排除、等等。 当我的 xds100v3n`t 目标时、我可以执行该程序、但当我移除它时、它确实会触发...

    此外、我移除了 GPIO34开关引脚上的910ohm 上拉电阻器、现在当我打开该开关时、它会将 GPIO34直接连接到 Vcc。

    还有其他建议吗?

    再次感谢!

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好!

    您能否共享您使用过的链接器 cmd 文件? 如果它已经存在于 rar 文件中、您能否将我指向该位置?

    以下是可能有用的常见问题解答- https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/878674/faq-flash---how-to-modify-an-application-from-ram-configuration-to-flash-configuration

    此致、

    Veena

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    这是文件->  

    /*
    //###########################################################################
    //
    // FILE:    F28069.cmd
    //
    // TITLE:   Linker Command File For F28069 Device
    //
    //###########################################################################
    // $TI Release: F2806x C/C++ Header Files and Peripheral Examples V135 $ 
    // $Release Date: Sep 8, 2012 $ 
    //###########################################################################
    */
    
    /* ======================================================
    // For Code Composer Studio V2.2 and later
    // ---------------------------------------
    // In addition to this memory linker command file,
    // add the header linker command file directly to the project.
    // The header linker command file is required to link the
    // peripheral structures to the proper locations within
    // the memory map.
    //
    // The header linker files are found in <base>\F2806x_headers\cmd
    //
    // For BIOS applications add:      F2806x_Headers_BIOS.cmd
    // For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
    ========================================================= */
    
    /* ======================================================
    // For Code Composer Studio prior to V2.2
    // --------------------------------------
    // 1) Use one of the following -l statements to include the
    // header linker command file in the project. The header linker
    // file is required to link the peripheral structures to the proper
    // locations within the memory map                                    */
    
    /* Uncomment this line to include file only for non-BIOS applications */
    /* -l F2806x_Headers_nonBIOS.cmd */
    
    /* Uncomment this line to include file only for BIOS applications */
    /* -l F2806x_Headers_BIOS.cmd */
    
    /* 2) In your project add the path to <base>\F2806x_headers\cmd to the
       library search path under project->build options, linker tab,
       library search path (-i). */
    /*========================================================= */
    
    /* Define the memory block start/length for the F2806x
       PAGE 0 will be used to organize program sections
       PAGE 1 will be used to organize data sections
    
       Notes:
             Memory blocks on F28069 are uniform (ie same
             physical memory) in both PAGE 0 and PAGE 1.
             That is the same memory region should not be
             defined for both PAGE 0 and PAGE 1.
             Doing so will result in corruption of program
             and/or data.
    
             Contiguous SARAM memory blocks can be combined
             if required to create a larger memory block.
    */
    
    MEMORY
    {
    PAGE 0 :   /* Program Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
       RAML0_1     : origin = 0x008000, length = 0x000C00     /* on-chip RAM block L0 and L1 */
       OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
    
       FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
       FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
       FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
       FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
       FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
       FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
       FLASHA_B    : origin = 0x3F0000, length = 0x007F80     /* on-chip FLASH */
       CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
       BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
       CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
    
       FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	 /* FPU Tables in Boot ROM */
       IQTABLES    : origin = 0x3FDC30, length = 0x000B50    /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FE780, length = 0x00008C    /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FE80C, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */
    
       ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
       RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
       VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
               /* Registers remain on PAGE1                                                  */
    
       BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
       RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
       RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
       RAML2_3     : origin = 0x008C00, length = 0x001400     /* on-chip RAM block L2 */
       RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
       RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
       RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
       RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
       RAML8       : origin = 0x012000, length = 0x001800     /* on-chip RAM block L8. From 0x13800 to 0x14000 is reserved for InstaSPIN */
       USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
    }
    
    /* Allocate sections to memory blocks.
       Note:
             codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                       execution when booting to flash
             ramfuncs  user defined section to store functions that will be copied from Flash into RAM
    */
    
    
    SECTIONS
    {
    
       /* Allocate program areas: */
       .cinit              : > FLASHA_B,   PAGE = 0
       .pinit              : > FLASHA_B,   PAGE = 0
       .text               : > FLASHA_B,   PAGE = 0
       codestart           : > BEGIN,      PAGE = 0
       ramfuncs            : LOAD = FLASHD,
                             RUN = RAML0_1,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             PAGE = 0
    
       csmpasswds          : > CSM_PWL_P0, PAGE = 0
       csm_rsvd            : > CSM_RSVD,   PAGE = 0
    
       /* Allocate uninitalized data sections: */
       .stack              : > RAMM0,      PAGE = 1
       .ebss               : > RAML2_3,    PAGE = 1
       .esysmem            : > RAML2_3,    PAGE = 1
    
       /* Initalized sections to go in Flash */
       /* For SDFlash to program these, they must be allocated to page 0 */
       .econst             : > FLASHA_B,   PAGE = 0
       .switch             : > FLASHA_B,   PAGE = 0
    
       /* Allocate IQ math areas: */
       IQmath              : > FLASHA_B,   PAGE = 0            /* Math Code */
       IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
       
       /* Allocate FPU math areas: */
       FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
       
       DMARAML5	           : > RAML5,      PAGE = 1
       DMARAML6	           : > RAML6,      PAGE = 1
       DMARAML7	           : > RAML7,      PAGE = 1
       DMARAML8	           : > RAML8,      PAGE = 1   
    
      /* Uncomment the section below if calling the IQNexp() or IQexp()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    
       }
       */
       /* Uncomment the section below if calling the IQNasin() or IQasin()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables3
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    
       }
       */
    
       /* .reset is a standard section used by the compiler.  It contains the */
       /* the address of the start of _c_int00 for C Code.  */
       /* When using the boot ROM this section and the CPU vector */
       /* table is not needed.  Thus the default type is set here to  */
       /* DSECT  */
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT
       vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

    这是 F28069M.cmd。 我n`t 某种原因无法上传。 抱歉、我在 zip 文件中忘记了它、因为我使用单独的笔记本电脑进行嵌入式开发。 这是一个高电压n`t、我不想使用主计算机。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    此外、 您在对.out 进行编程或运行时是否面临此问题? 您能否详细介绍所面临的错误

    此致、

    Veena

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    我n`t 在控制器上执行项目、但它本身不工作。 当我将项目加载到 UC 时、它会运行、但当我重启 UC 时、一切都不会发生...

    我向 ramfuncs 添加了 CSI 中断-运气不好。 我的闪存定义不在 main.c 中、而是在 system.c 中是否可能会导致此问题?

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您能否查看我先前分享的常见问题解答? 有一节介绍 了独立运行时发现的常见问题

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/878674/faq-flash---how-to-modify-an-application-from-ram-configuration-to-flash-configuration

    此致、

    Veena

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    还可以! 我会尽快返回反馈!