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器件型号：TMS320F28335 大家好、
引导加载程序由客户编写。
在烧录 hex 文件后、引导程序可与上部计算机配合、正常跳转到应用程序。 但是、一旦修改了应用程序、就会出现以下问题：
1) 1) 应用程序在使用闪存库函数运行时将卡住
2) 2) 它在添加代码后也会卡住
应用程序 cmd 文件如下所示：
/* //########################################################################### // // FILE: F28335.cmd // // TITLE: Linker Command File For F28335 Device // //########################################################################### // $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ // $Release Date: November 1, 2016 $ // $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in <base>\DSP2833x_Headers\cmd // // For BIOS applications add: DSP2833x_Headers_BIOS.cmd // For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd ========================================================= */ /* ====================================================== // For Code Composer Studio prior to V2.2 // -------------------------------------- // 1) Use one of the following -l statements to include the // header linker command file in the project. The header linker // file is required to link the peripheral structures to the proper // locations within the memory map */ /* Uncomment this line to include file only for non-BIOS applications */ /* -l DSP2833x_Headers_nonBIOS.cmd */ /* Uncomment this line to include file only for BIOS applications */ /* -l DSP2833x_Headers_BIOS.cmd */ /* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the library search path under project->build options, linker tab, library search path (-i). /*========================================================= */ /* Define the memory block start/length for the F28335 PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F28335 are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. L0/L1/L2 and L3 memory blocks are mirrored - that is they can be accessed in high memory or low memory. For simplicity only one instance is used in this linker file. Contiguous SARAM memory blocks can be combined if required to create a larger memory block. */ MEMORY { PAGE 0: /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ RAML0 : origin = 0x008000, length = 0x002000 /* on-chip RAM block L0 */ RAML1 : origin = 0x00A000, length = 0x000800 /* on-chip RAM block L1 */ RAML2 : origin = 0x00A800, length = 0x000800 /* on-chip RAM block L2 */ ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ // FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ // FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ // FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ // FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ // FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ // FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ // FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ BEGIN : origin = 0x308000, length = 0x000002 APP_FLASH : origin = 0x308002, length = 0x020000 /* on-chip FLASH */ CSM_RSVD : origin = 0x328002, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ CSM_PWL : origin = 0x328078, length = 0x000008 IAPDATE_FLASH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ BOOST_FLASH : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMLH : origin = 0x00B000, length = 0x004000 /* on-chip RAM block L3 */ // RAMLH : origin = 0x00C000, length = 0x003000 /* on-chip RAM block L1 */ // RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ // RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ // RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ // RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ /*** Custom Defines Registers ***/ PARAREG : origin = 0x00F000, length = 0x000200 MONIREG : origin = 0x00F200, length = 0x000D00 } /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ .cinit : > APP_FLASH PAGE = 0 .pinit : > APP_FLASH, PAGE = 0 .text : > APP_FLASH PAGE = 0 codestart : > BEGIN PAGE = 0 ramfuncs : LOAD = APP_FLASH, RUN = RAML0, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), LOAD_SIZE(_RamfuncsLoadSize), PAGE = 0 Flash28_API: { -lFlash28335_API_V210.lib(.econst) -lFlash28335_API_V210.lib(.text) } LOAD = APP_FLASH, RUN = RAML0, LOAD_START(_Flash28_API_LoadStart), LOAD_END(_Flash28_API_LoadEnd), RUN_START(_Flash28_API_RunStart), PAGE = 0 csmpasswds : > CSM_PWL PAGE = 0 csm_rsvd : > CSM_RSVD PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAMM1 PAGE = 1 .ebss : > RAMLH PAGE = 1 .esysmem : > RAMM1 PAGE = 1 /* Initalized sections go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > APP_FLASH PAGE = 0 .switch : > APP_FLASH PAGE = 0 /* Allocate IQ math areas: */ IQmath : > APP_FLASH PAGE = 0 /* Math Code */ IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD /* Uncomment the section below if calling the IQNexp() or IQexp() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD { IQmath.lib<IQNexpTable.obj> (IQmathTablesRam) } */ FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD /* Allocate DMA-accessible RAM sections: */ DMARAML4 : > RAMLH, PAGE = 1 DMARAML5 : > RAMLH, PAGE = 1 DMARAML6 : > RAMLH, PAGE = 1 DMARAML7 : > RAMLH, PAGE = 1 /* Allocate 0x400 of XINTF Zone 7 to storing data */ ZONE7DATA : > ZONE7B, PAGE = 1 /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS PAGE = 0, TYPE = DSECT /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD } /* //=========================================================================== // End of file. //=========================================================================== */ boot 程序 cmd文件 /* //########################################################################### // // FILE: F28335.cmd // // TITLE: Linker Command File For F28335 Device // //########################################################################### // $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ // $Release Date: November 1, 2016 $ // $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in <base>\DSP2833x_Headers\cmd // // For BIOS applications add: DSP2833x_Headers_BIOS.cmd // For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd ========================================================= */ /* ====================================================== // For Code Composer Studio prior to V2.2 // -------------------------------------- // 1) Use one of the following -l statements to include the // header linker command file in the project. The header linker // file is required to link the peripheral structures to the proper // locations within the memory map */ /* Uncomment this line to include file only for non-BIOS applications */ /* -l DSP2833x_Headers_nonBIOS.cmd */ /* Uncomment this line to include file only for BIOS applications */ /* -l DSP2833x_Headers_BIOS.cmd */ /* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the library search path under project->build options, linker tab, library search path (-i). /*========================================================= */ /* Define the memory block start/length for the F28335 PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F28335 are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. L0/L1/L2 and L3 memory blocks are mirrored - that is they can be accessed in high memory or low memory. For simplicity only one instance is used in this linker file. Contiguous SARAM memory blocks can be combined if required to create a larger memory block. */ MEMORY { PAGE 0: /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ RAML0 : origin = 0x008000, length = 0x002000 /* on-chip RAM block L0 */ RAML1 : origin = 0x00A000, length = 0x000800 /* on-chip RAM block L1 */ RAML2 : origin = 0x00A800, length = 0x000800 /* on-chip RAM block L2 */ // RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ //BEGIN : origin = 0x300000, length = 0x000002 APP_FLASH : origin = 0x300002, length = 0x020000 /* on-chip FLASH */ IAPDATE_FLASH : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ BEGIN : origin = 0x338000, length = 0x000002 BOOST_FLASH : origin = 0x338002, length = 0x007F80 /* on-chip FLASH */ CSM_RSVD : origin = 0x33FF82, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ CSM_PWL : origin = 0x33FFFA, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMLH : origin = 0x00B000, length = 0x004000 /* on-chip RAM block L3 */ // RAMLH : origin = 0x00C000, length = 0x003000 /* on-chip RAM block L1 */ // RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ // RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ // RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ // RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */ /*** Custom Defines Registers ***/ PARAREG : origin = 0x00F000, length = 0x000200 MONIREG : origin = 0x00F200, length = 0x000D00 } /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ .cinit : > BOOST_FLASH PAGE = 0 .pinit : > BOOST_FLASH, PAGE = 0 .text : > BOOST_FLASH PAGE = 0 codestart : > BEGIN PAGE = 0 ramfuncs : LOAD = BOOST_FLASH, RUN = RAML0, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), LOAD_SIZE(_RamfuncsLoadSize), PAGE = 0 /* The Flash API functions can be grouped together as shown below. The defined symbols _Flash28_API_LoadStart, _Flash28_API_LoadEnd and _Flash28_API_RunStart are used to copy the API functions out of flash memory and into SARAM */ Flash28_API: { -lFlash28335_API_V210.lib(.econst) -lFlash28335_API_V210.lib(.text) } LOAD = BOOST_FLASH, RUN = RAML0, LOAD_START(_Flash28_API_LoadStart), LOAD_END(_Flash28_API_LoadEnd), RUN_START(_Flash28_API_RunStart), PAGE = 0 csmpasswds : > CSM_PWL PAGE = 0 csm_rsvd : > CSM_RSVD PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAMM1 PAGE = 1 .ebss : > RAMLH PAGE = 1 .esysmem : > RAMM1 PAGE = 1 /* Initalized sections go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > BOOST_FLASH PAGE = 0 .switch : > BOOST_FLASH PAGE = 0 /* Allocate DMA-accessible RAM sections: */ DMARAML4 : > RAMLH, PAGE = 1 DMARAML5 : > RAMLH, PAGE = 1 DMARAML6 : > RAMLH, PAGE = 1 DMARAML7 : > RAMLH, PAGE = 1 /* Allocate 0x400 of XINTF Zone 7 to storing data */ ZONE7DATA : > ZONE7B, PAGE = 1 /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS PAGE = 0, TYPE = DSECT /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD } /* //=========================================================================== // End of file. //===========================================================================
您能帮助检查这个案例吗？ 谢谢。
此致、
切里
