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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/649193/tlc551-connecting-shorting-pins-3-and-7
您好，
输出引脚是否可以与放电引脚短路？ 如果短接在一起，请注意在TI的晶体管级等效原理图中，如果条件Vdd > Vthresh*2保持，在通过放电晶体管从高输出转换到低输出的过程中，可能会有大量的直通(交叉)电流。
是否有任何种类的先断后断电路(原理图中未显示)可能会阻止此情况发生？
提前感谢。
